Icestorm: PACIB measurements

Code:

  pacib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	? int output thing (e9)	? int retires (ef)
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000

Test 2: Latency 1->1

Code:

  pacib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  pacib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	72636	20522	20522	21566	1450132	21698	11137	22057	20453	30100
30204	72627	20525	20525	21566	1449810	21681	11121	22052	20448	30100
30204	72580	20524	20524	21547	1449858	21670	11121	22066	20449	30100
30204	72679	20545	20545	21607	1449419	21655	11114	22109	20458	30100
30204	72685	20523	20523	21585	1448383	21567	11050	22086	20456	30100
30204	72627	20530	20530	21572	1448177	21570	11054	22090	20460	30100
30204	72680	20537	20537	21596	1448342	21568	11052	22063	20451	30100
30204	72583	20525	20525	21549	1448260	21575	11067	22052	20449	30100
30204	72630	20526	20526	21569	1449270	21648	11105	21120	20275	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	20101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	70029	20021	20021	20022	1429189	20022	10024	20028	20011	30010
30024	70029	20021	20021	20022	1429439	20047	10041	20028	20011	30010
30024	70029	20021	20021	20022	1429208	20022	10024	20028	20011	30010
30024	70029	20021	20021	20022	1429208	20022	10024	20028	20011	30010
30024	70029	20021	20021	20022	1429208	20022	10024	20028	20011	30010
30024	70029	20021	20021	20022	1429208	20022	10024	20028	20011	30010
30024	70029	20021	20021	20022	1429208	20022	10024	20028	20011	30010
30024	70029	20021	20021	20022	1429208	20022	10024	20028	20011	30010
30024	70029	20021	20021	20022	1429208	20022	10024	20028	20011	30010
30024	70029	20021	20021	20022	1429181	20020	10020	20020	20011	30010

Test 4: throughput

Count: 8

Code:

  pacib x0, x8
  pacib x1, x8
  pacib x2, x8
  pacib x3, x8
  pacib x4, x8
  pacib x5, x8
  pacib x6, x8
  pacib x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	160030	80201	80201	80202	0	1360566	0	0	80219	200	0	0	200	80101	80100
80204	160030	80201	80201	80202	0	1360481	0	0	80202	200	0	0	200	80101	80100
80204	160030	80201	80201	80202	0	1360481	0	0	80202	200	0	0	200	80101	80100
80204	160030	80201	80201	80202	0	1360481	0	0	80202	200	0	0	200	80101	80100
80205	160060	80209	80209	80219	0	1360430	0	0	80202	200	0	0	200	80101	80100
80204	160030	80201	80201	80202	0	1360481	0	0	80202	200	0	0	200	80101	80100
80204	160030	80201	80201	80202	0	1360481	0	0	80202	200	0	0	200	80101	80100
80204	160030	80201	80201	80202	0	1360481	0	0	80202	200	0	0	200	80101	80100
80205	160064	80211	80211	80220	0	1360481	0	0	80202	200	0	0	200	80101	80100
80205	160064	80211	80211	80220	0	1360481	0	0	80202	200	0	0	200	80101	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	160030	80021	80021	0	0	80022	0	1359880	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1360040	80040	20	20	80021	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	0	80020	0	1360048	80040	20	20	80011	80010

PACIB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations