Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
casah w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 4.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 74007 | 34588 | 3010 | 1 | 0 | 3009 | 0 | 0 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34279 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34269 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34338 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34541 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34259 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15036 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34406 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34546 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34435 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34519 | 3001 | 1 | 0 | 3000 | 0 | 0 | 3000 | 15037 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
Code:
casah w0, w1, [x6] add x6, x6, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 7.0058
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 50208 | 70247 | 41834 | 11786 | 30048 | 11786 | 30003 | 42926 | 279980 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
| 50204 | 70060 | 44267 | 14266 | 30001 | 14265 | 30003 | 42866 | 279875 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
| 50204 | 70054 | 44267 | 14266 | 30001 | 14265 | 30003 | 42860 | 279890 | 44268 | 20201 | 30003 | 20223 | 60072 | 13056 | 30000 | 0 | 20100 |
| 50204 | 70054 | 44267 | 14266 | 30001 | 14265 | 30003 | 42860 | 279890 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
| 50204 | 70060 | 44267 | 14266 | 30001 | 14265 | 30003 | 42861 | 279900 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
| 50204 | 70054 | 44267 | 14266 | 30001 | 14265 | 30003 | 42862 | 279895 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
| 50204 | 70060 | 44267 | 14266 | 30001 | 14265 | 30003 | 42890 | 279924 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
| 50204 | 70051 | 44267 | 14266 | 30001 | 14265 | 30003 | 42890 | 279921 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
| 50204 | 70051 | 44267 | 14266 | 30001 | 14265 | 30003 | 42861 | 279801 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
| 50204 | 70051 | 44267 | 14266 | 30001 | 14265 | 30003 | 42898 | 280053 | 44268 | 20201 | 30003 | 20201 | 60006 | 14166 | 30000 | 0 | 20100 |
Result (median cycles for code): 7.0051
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 50028 | 70325 | 41744 | 11696 | 30048 | 11696 | 30003 | 42639 | 280241 | 44178 | 20021 | 30003 | 20020 | 60000 | 0 | 14167 | 30000 | 0 | 20010 |
| 50024 | 70060 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
| 50024 | 70054 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
| 50024 | 70070 | 44176 | 14176 | 30000 | 14175 | 30000 | 42615 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
| 50024 | 70054 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
| 50024 | 70054 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
| 50024 | 70054 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
| 50024 | 70054 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
| 50024 | 70054 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
| 50024 | 70054 | 44176 | 14176 | 30000 | 14175 | 30000 | 42613 | 280114 | 44175 | 20020 | 30000 | 20020 | 60000 | 0 | 14166 | 30000 | 0 | 20010 |
Code:
casah w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 22.0039
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 40207 | 220152 | 33471 | 3435 | 0 | 30036 | 1771 | 0 | 30003 | 845667 | 2698454 | 34268 | 10201 | 30003 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
| 40204 | 220039 | 38398 | 8397 | 0 | 30001 | 4265 | 0 | 30003 | 845667 | 2698476 | 34268 | 10201 | 30003 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
| 40204 | 220088 | 38431 | 8430 | 0 | 30001 | 4265 | 0 | 30003 | 845677 | 2698503 | 34268 | 10201 | 30003 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
| 40204 | 220036 | 38429 | 8428 | 0 | 30001 | 4265 | 0 | 30036 | 446172 | 2698924 | 32334 | 10212 | 30036 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
| 40204 | 220036 | 38429 | 8428 | 0 | 30001 | 4265 | 0 | 30003 | 845667 | 2698476 | 34268 | 10201 | 30003 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
| 40204 | 220036 | 38429 | 8428 | 0 | 30001 | 4265 | 0 | 30003 | 845667 | 2698476 | 34268 | 10201 | 30003 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
| 40204 | 220036 | 38429 | 8428 | 0 | 30001 | 4265 | 0 | 30003 | 845667 | 2698476 | 34268 | 10201 | 30003 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
| 40204 | 220036 | 38429 | 8428 | 0 | 30001 | 4265 | 0 | 30003 | 845667 | 2698476 | 34268 | 10201 | 30003 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
| 40204 | 220036 | 38429 | 8428 | 0 | 30001 | 4265 | 0 | 30003 | 845877 | 2699235 | 34268 | 10201 | 30003 | 10212 | 60072 | 0 | 6462 | 30000 | 0 | 10100 |
| 40204 | 220039 | 38429 | 8428 | 0 | 30001 | 4265 | 0 | 30003 | 845667 | 2698476 | 34268 | 10201 | 30003 | 10201 | 60006 | 0 | 8328 | 30000 | 0 | 10100 |
Result (median cycles for code): 22.0046
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 40029 | 220285 | 33414 | 3344 | 30070 | 1682 | 30003 | 845466 | 2699019 | 34178 | 10021 | 30003 | 10020 | 60000 | 0 | 8329 | 30000 | 0 | 10010 |
| 40024 | 220054 | 38339 | 8339 | 30000 | 4175 | 30000 | 845462 | 2699007 | 34175 | 10020 | 30000 | 10020 | 60000 | 0 | 8329 | 30000 | 0 | 10010 |
| 40024 | 220054 | 38339 | 8339 | 30000 | 4175 | 30036 | 426994 | 2699247 | 32150 | 10032 | 30036 | 10020 | 60000 | 0 | 8329 | 30000 | 0 | 10010 |
| 40025 | 220120 | 34337 | 4307 | 30030 | 2164 | 30000 | 845462 | 2698985 | 34175 | 10020 | 30000 | 10020 | 60000 | 0 | 8329 | 30000 | 0 | 10010 |
| 40024 | 220054 | 38339 | 8339 | 30000 | 4175 | 30000 | 845462 | 2699009 | 34175 | 10020 | 30000 | 10026 | 60036 | 0 | 8330 | 30000 | 0 | 10011 |
| 40024 | 220044 | 38340 | 8340 | 30000 | 4175 | 30000 | 845422 | 2698677 | 34175 | 10020 | 30000 | 10032 | 60072 | 0 | 4411 | 30000 | 0 | 10010 |
| 40024 | 220045 | 38340 | 8340 | 30000 | 4175 | 30000 | 845422 | 2698681 | 34175 | 10020 | 30000 | 10020 | 60000 | 0 | 8330 | 30000 | 0 | 10010 |
| 40026 | 220074 | 34557 | 4522 | 30035 | 2272 | 30000 | 845422 | 2698677 | 34175 | 10020 | 30000 | 10020 | 60000 | 0 | 8330 | 30000 | 0 | 10010 |
| 40024 | 220044 | 38340 | 8340 | 30000 | 4175 | 30000 | 845422 | 2698671 | 34175 | 10020 | 30000 | 10020 | 60000 | 0 | 8330 | 30000 | 0 | 10010 |
| 40024 | 220044 | 38340 | 8340 | 30000 | 4175 | 30000 | 845422 | 2698677 | 34175 | 10020 | 30000 | 10032 | 60072 | 0 | 6385 | 30000 | 0 | 10010 |