Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STLXR (64-bit)

Test 1: uops

Code:

  stlxr w0, x1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	3159	1019	1	1018	1000	51855	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000
1004	3040	1001	1	1000	1000	51713	1000	1000	2000	1	1000

Test 2: throughput

Code:

  stlxr w0, x1, [x6]
  add x6, x6, 16

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.2396

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20214	33665	20533	10353	10180	10352	10003	35477	365390	20106	10203	10003	10203	20006	10004	10000	10100
20204	32343	20103	10103	10000	10102	10002	35467	363604	20104	10202	10002	10202	20004	10003	10000	10100
20204	32366	20104	10104	10000	10103	10002	35467	363644	20104	10202	10002	10202	20004	10003	10000	10100
20204	32343	20103	10103	10000	10102	10002	35467	363718	20104	10202	10002	10202	20004	10003	10000	10100
20204	32344	20103	10103	10000	10102	10002	35467	363846	20104	10202	10002	10202	20004	10003	10000	10100
20204	32346	20103	10103	10000	10102	10002	35467	363750	20104	10202	10002	10202	20004	10003	10000	10100
20204	32330	20103	10103	10000	10102	10002	35467	363603	20104	10202	10002	10202	20004	10003	10000	10100
20204	32330	20103	10103	10000	10102	10002	35467	363773	20104	10202	10002	10202	20004	10003	10000	10100
20204	32359	20103	10103	10000	10102	10002	35467	364608	20104	10202	10002	10202	20004	10003	10000	10100
20204	32326	20103	10103	10000	10102	10002	35467	363868	20104	10202	10002	10202	20004	10003	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.2567

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20034	33827	20447	10267	10180	10266	10002	35242	367114	20014	10022	10002	10020	20000	10001	10000	10010
20024	32570	20011	10011	10000	10010	10000	35235	366662	20010	10020	10000	10020	20000	10001	10000	10010
20024	32563	20011	10011	10000	10010	10000	35235	366376	20010	10020	10000	10020	20000	10001	10000	10010
20024	32580	20011	10011	10000	10010	10000	35235	366746	20010	10020	10000	10020	20000	10001	10000	10010
20024	32586	20011	10011	10000	10010	10034	35583	369345	20078	10054	10034	10020	20000	10001	10000	10010
20024	32586	20011	10011	10000	10010	10000	35235	366589	20010	10020	10000	10020	20000	10001	10000	10010
20024	32569	20011	10011	10000	10010	10000	35235	366361	20010	10020	10000	10020	20000	10001	10000	10010
20024	32554	20011	10011	10000	10010	10000	35235	367336	20010	10020	10000	10020	20000	10001	10000	10010
20024	32516	20011	10011	10000	10010	10000	35235	365615	20010	10020	10000	10052	20064	10033	10000	10010
20024	32489	20011	10011	10000	10010	10000	35235	366127	20010	10020	10000	10020	20000	10001	10000	10010

Test 3: throughput

Code:

  stlxr w0, x1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10205	30153	10119	101	10018	100	10000	300	528855	10100	200	10004	200	20008	1	10000	100
10204	30098	10101	101	10000	100	10144	321	533949	10250	206	10188	200	20008	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	100
10204	30063	10101	101	10000	100	10000	300	529665	10100	200	10004	200	20008	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	100
10204	30047	10101	101	10000	100	10036	300	529321	10136	200	10048	200	20008	1	10000	100
10204	30047	10101	101	10000	100	10000	300	528855	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10025	30280	10029	11	10018	10	10000	30	528927	10010	20	10004	20	20008	1	10000	10
10024	30047	10011	11	10000	10	10000	30	528981	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10
10024	30040	10011	11	10000	10	10000	30	528855	10010	20	10000	20	20000	1	10000	10