Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (immediate, 32-bit)

Test 1: uops

Code:

  sub w0, w0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000
100410301001100110002560310001000100010011000

Test 2: Latency 1->2

Code:

  sub w0, w0, #3
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082593111010710214102141000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100
10204100301010110101101072595391010710212102121000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282596281002810036100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010
10024100301002110021100202595911002010020100201001110010

Test 3: throughput

Count: 8

Code:

  sub w0, w8, #3
  sub w1, w8, #3
  sub w2, w8, #3
  sub w3, w8, #3
  sub w4, w8, #3
  sub w5, w8, #3
  sub w6, w8, #3
  sub w7, w8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802042684680115801150801202403608012080224802248001580100
802042676080115801150801202403608012080224802228001480100
802042673780115801150801202403608012080224802248001580100
802042673780115801150801202403608012080224802248001580100
802042673780115801150801202403608012080224802248001580100
802042673780115801150801202403608012080224802248001580100
802042673780115801150801202403608012080224802248001580100
802042673780115801150801202403608012080224802248001580100
802042673780115801150801202403608012080224802248001580100
802042673780115801150801202403608012080224802248001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024279628003980039800442668128004280044800208001180010
80024267738002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010
80024267138002180021800202774048002080020800208001180010