Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BL

Test 1: uops

Code:

  bl .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	map int uop (7c)	? int output thing (e9)
1004	3076	1	1	1000	1
1004	2037	1	1	1000	1
1004	2202	1	1	1000	1
1004	2244	1	1	1000	1
1004	2171	1	1	1000	1
1004	2084	1	1	1000	1
1004	2129	1	1	1000	1
1004	2307	1	1	1000	1
1004	2170	1	1	1000	1
1004	1983	1	1	1000	1

Test 2: throughput

Count: 8

Code:

  bl .+4
  bl .+4
  bl .+4
  bl .+4
  bl .+4
  bl .+4
  bl .+4
  bl .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0492

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	85350	101	101	100	300	100	80206	200	1	100
80204	84117	101	101	100	300	100	80206	200	1	100
80204	83918	101	101	100	300	100	80217	200	1	100
80204	83935	101	101	100	300	100	80206	200	1	100
80204	83953	101	101	100	300	100	80201	200	1	100
80204	83912	101	101	100	300	100	80206	200	1	100
80204	83969	101	101	100	300	100	80206	200	1	100
80204	83939	101	101	100	300	100	80201	200	1	100
80204	83938	101	101	100	300	100	80201	200	1	100
80205	84142	101	101	100	300	100	80206	200	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.9747

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	241585	11	11	0	10	0	30	0	0	10	80037	0	0	20	1	10
80024	238729	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10
80024	237791	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10
80024	238358	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10
80025	238410	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10
80024	238253	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10
80024	238248	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10
80024	238409	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10
80024	238412	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10
80024	239843	11	11	0	10	0	30	0	0	10	80021	0	0	20	1	10