Icestorm: LDRSB (pre-index, 64-bit) measurements

Code:

  ldrsb x0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1228	2033	1020	1013	1036	1000	20606	17363	2000	1000	1000	1000	1000	1001	1000	1000
2004	1075	2001	1001	1000	1000	1000	21278	17395	2000	1000	1000	1000	1000	1001	1000	1000
2004	1066	2001	1001	1000	1000	1000	21230	17413	2000	1000	1000	1000	1000	1001	1000	1000
2004	1122	2001	1001	1000	1000	1000	20665	18216	2000	1000	1000	1000	1000	1001	1000	1000
2004	1079	2001	1001	1000	1000	1000	21526	17647	2000	1000	1000	1000	1000	1001	1000	1000
2004	1078	2001	1001	1000	1000	1000	21224	17625	2000	1000	1000	1000	1000	1001	1000	1000
2004	1119	2001	1001	1000	1000	1000	21376	17631	2000	1000	1000	1000	1000	1001	1000	1000
2004	1118	2001	1001	1000	1000	1000	21300	17986	2000	1000	1000	1000	1000	1001	1000	1000
2004	1098	2001	1001	1000	1000	1000	21404	17648	2000	1000	1000	1000	1000	1001	1000	1000
2004	1101	2001	1001	1000	1000	1000	20856	17710	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0101

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71253	50161	40156	10005	40247	10002	1850911	534900	50108	40211	10003	70292	10015	40015	10000	40100
50204	70141	50104	40104	10000	40106	10003	1850901	534963	50109	40212	10004	70221	10004	40004	10000	40100
50204	70164	50104	40104	10000	40106	10003	1851630	535206	50109	40212	10004	70221	10004	40004	10000	40100
50204	70146	50104	40104	10000	40106	10003	1851279	535088	50109	40212	10004	70221	10004	40004	10000	40100
50204	70139	50104	40104	10000	40106	10003	1851846	535272	50109	40212	10004	70221	10004	40004	10000	40100
50204	70207	50105	40105	10000	40106	10003	1852720	535501	50109	40212	10004	70221	10004	40004	10000	40100
50204	70101	50104	40104	10000	40106	10012	1853530	535703	50152	40251	10013	70221	10004	40004	10000	40100
50204	70129	50104	40104	10000	40106	10003	1852116	535361	50109	40212	10004	70221	10004	40004	10000	40100
50204	70121	50104	40104	10000	40106	10003	1850982	534986	50109	40212	10004	70221	10004	40004	10000	40100
50204	70101	50104	40104	10000	40106	10003	1850469	534815	50109	40212	10004	70221	10004	40004	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0248

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71433	50076	40071	10005	40156	10003	1852260	535713	50019	40032	10004	70020	10000	40007	10000	40010
50024	70186	50017	40017	10000	40010	10000	1852037	535621	50010	40020	10000	70112	10015	40019	10000	40010
50024	70184	50018	40018	10000	40010	10000	1851875	535567	50010	40020	10000	70020	10000	40007	10000	40010
50024	70160	50017	40017	10000	40010	10000	1851875	535567	50010	40020	10000	70020	10000	40007	10000	40010
50024	70160	50017	40017	10000	40010	10009	1853697	535813	50053	40059	10010	70020	10000	40007	10000	40010
50024	70202	50017	40017	10000	40010	10000	1852253	535693	50010	40020	10000	70020	10000	40007	10000	40010
50024	70160	50017	40017	10000	40010	10000	1851875	535567	50010	40020	10000	70020	10000	40007	10000	40010
50024	70202	50017	40017	10000	40010	10000	1852496	535774	50010	40020	10000	70020	10000	40007	10000	40010
50024	70185	50017	40017	10000	40010	10000	1852469	535763	50010	40020	10000	70020	10000	40007	10000	40010
50024	70177	50017	40017	10000	40010	10000	1852199	535675	50010	40020	10000	70020	10000	40007	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsb x0, [x6, #8]!
  ldrsb x0, [x7, #8]!
  ldrsb x0, [x8, #8]!
  ldrsb x0, [x9, #8]!
  ldrsb x0, [x10, #8]!
  ldrsb x0, [x11, #8]!
  ldrsb x0, [x12, #8]!
  ldrsb x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44238	160423	80312	80111	80315	80011	240578	638086	160123	80212	80012	80212	80012	80009	80000	80100
160204	43228	160111	80109	80002	80112	80011	240485	644989	160123	80212	80012	80212	80012	80009	80000	80100
160204	43215	160109	80109	80000	80112	80011	240485	646411	160123	80212	80012	80254	80054	80051	80000	80100
160204	43215	160109	80109	80000	80112	80009	240485	644459	160121	80212	80012	80212	80012	80009	80000	80100
160204	43218	160109	80109	80000	80112	80011	240485	642143	160123	80212	80012	80212	80012	80009	80000	80100
160204	43216	160109	80109	80000	80112	80010	240485	640554	160122	80212	80012	80212	80012	80009	80000	80100
160204	43222	160109	80109	80000	80112	80011	240485	642721	160123	80212	80012	80212	80012	80009	80000	80100
160204	43215	160109	80109	80000	80112	80011	240485	647931	160123	80212	80012	80212	80012	80009	80000	80100
160204	43219	160110	80109	80001	80112	80010	240485	635198	160122	80212	80012	80212	80012	80009	80000	80100
160204	43219	160110	80109	80001	80112	80012	240626	640324	160124	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44329	160335	80222	80113	80225	80053	240689	641231	160117	80074	80054	80032	80012	80009	80000	80010
160024	43231	160011	80011	80000	80010	80000	240272	641282	160010	80020	80000	80020	80000	80001	80000	80010
160024	43222	160011	80011	80000	80010	80000	240272	634707	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240272	637580	160010	80020	80000	80020	80000	80001	80000	80010
160024	43224	160011	80011	80000	80010	80000	240272	639337	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240272	640266	160010	80020	80000	80020	80000	80001	80000	80010
160025	43621	160091	80061	80030	80064	80054	240840	584379	160118	80074	80054	80030	80010	80007	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	646451	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240331	644028	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	643644	160010	80020	80000	80020	80000	80001	80000	80010

LDRSB (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations