Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

B.cc (not taken)

Test 1: uops

Code:

  b.eq .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)
10045116351435144629116823894446710891
100467410231023103230931031104510001
100461210011001100030001000100010001
100461210011001100030001000100010001
100461210011001100030001000100010001
100461210011001100030001000100010001
100461210011001100030001000100010001
100461210011001100030001000100010001
100461210011001100030001000100010001
100461210011001100030001000100010001

Test 2: throughput

Count: 8

Code:

  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5836

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204547328447384473864222419118058280834805041100
80204467878016680166802012408338018180307802181100
80204466878010980109801122413848041180591802121100
80204466878010980109801122404928011280212802121100
80204466878010980109801122404928011280212802121100
80204466878010980109801122404928011280212802121100
80204466878010980109801122404928011280212802121100
80204466878010980109801122404928011280212802121100
80204466878010980109801122404928011280212802121100
80204466878010980109801122404928011280212802121100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5837

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024119785119038119038135958248824829358372782400110
8002448146808858088581286242621808658112280161110
8002446747800448004480059240204800598008180081110
8002446743800438004380056240156800438006180061110
8002446733800368003680043242664808808112080081110
8002446743800438004380056240204800598008180081110
8002446747800448004480059240441801428018780076110
8002446747800448004480059240204800598008180081110
8002446747800448004480059240204800598008180081110
8002446747800448004480059240204800598008180081110