Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

B.cc (not taken)

Test 1: uops

Code:

  b.eq .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	5116	3514	3514	4629	11682	3894	4467	1089	1
1004	674	1023	1023	1032	3093	1031	1045	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1
1004	612	1001	1001	1000	3000	1000	1000	1000	1

Test 2: throughput

Count: 8

Code:

  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4
  b.eq .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5836

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	54732	84473	84473	86422	241911	80582	80834	80504	1	100
80204	46787	80166	80166	80201	240833	80181	80307	80218	1	100
80204	46687	80109	80109	80112	241384	80411	80591	80212	1	100
80204	46687	80109	80109	80112	240492	80112	80212	80212	1	100
80204	46687	80109	80109	80112	240492	80112	80212	80212	1	100
80204	46687	80109	80109	80112	240492	80112	80212	80212	1	100
80204	46687	80109	80109	80112	240492	80112	80212	80212	1	100
80204	46687	80109	80109	80112	240492	80112	80212	80212	1	100
80204	46687	80109	80109	80112	240492	80112	80212	80212	1	100
80204	46687	80109	80109	80112	240492	80112	80212	80212	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5837

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	119785	119038	119038	135958	248824	82935	83727	82400	1	10
80024	48146	80885	80885	81286	242621	80865	81122	80161	1	10
80024	46747	80044	80044	80059	240204	80059	80081	80081	1	10
80024	46743	80043	80043	80056	240156	80043	80061	80061	1	10
80024	46733	80036	80036	80043	242664	80880	81120	80081	1	10
80024	46743	80043	80043	80056	240204	80059	80081	80081	1	10
80024	46747	80044	80044	80059	240441	80142	80187	80076	1	10
80024	46747	80044	80044	80059	240204	80059	80081	80081	1	10
80024	46747	80044	80044	80059	240204	80059	80081	80081	1	10
80024	46747	80044	80044	80059	240204	80059	80081	80081	1	10