Icestorm: LDR (post-index, 64-bit) measurements

Code:

  ldr x0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1369	2073	1043	1030	1042	1000	20877	17568	2000	1000	1000	1000	1000	1001	1000	1000
2004	1067	2001	1001	1000	1000	1000	21107	17698	2000	1000	1000	1000	1000	1001	1000	1000
2004	1078	2001	1001	1000	1000	1000	21133	17587	2000	1000	1000	1000	1000	1001	1000	1000
2004	1125	2001	1001	1000	1000	1000	21053	17628	2000	1000	1000	1000	1000	1001	1000	1000
2004	1068	2001	1001	1000	1000	1000	20807	18347	2000	1000	1000	1000	1000	1001	1000	1000
2004	1100	2001	1001	1000	1000	1000	21363	17811	2000	1000	1000	1000	1000	1001	1000	1000
2004	1082	2001	1001	1000	1000	1000	20788	18256	2000	1000	1000	1000	1000	1001	1000	1000
2004	1100	2001	1001	1000	1000	1000	20932	18349	2000	1000	1000	1000	1000	1001	1000	1000
2004	1084	2001	1001	1000	1000	1000	21073	18867	2000	1000	1000	1000	1000	1001	1000	1000
2004	1094	2001	1001	1000	1000	1000	20631	18526	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0101

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71398	50166	40161	10005	40247	10003	1850020	534564	50109	40212	10004	70221	10004	40004	10000	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534676	50109	40212	10004	70221	10004	40004	10000	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534676	50109	40212	10004	70221	10004	40004	10000	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534676	50109	40212	10004	70221	10004	40004	10000	40100
50204	70115	50104	40104	10000	40106	10003	1850172	534676	50109	40212	10004	70221	10004	40004	10000	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534676	50109	40212	10004	70221	10004	40004	10000	40100
50205	70181	50117	40115	10002	40140	10003	1850658	534834	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70293	10014	40016	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0159

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71311	50071	40066	10005	40156	10003	1851887	535414	50019	40032	10004	70020	10000	40007	10000	40010
50024	70162	50017	40017	10000	40010	10000	1851875	535468	50010	40020	10000	70020	10000	40006	10000	40010
50024	70153	50016	40016	10000	40010	10000	1851686	535419	50010	40020	10000	70020	10000	40006	10000	40010
50024	70153	50016	40016	10000	40010	10000	1851686	535419	50010	40020	10000	70020	10000	40006	10000	40010
50024	70153	50016	40016	10000	40010	10000	1851686	535419	50010	40020	10000	70020	10000	40006	10000	40010
50024	70153	50016	40016	10000	40010	10000	1851686	535419	50010	40020	10000	70020	10000	40006	10000	40010
50024	70153	50016	40016	10000	40010	10000	1851686	535419	50010	40020	10000	70020	10000	40006	10000	40010
50024	70153	50016	40016	10000	40010	10000	1851686	535419	50010	40020	10000	70020	10000	40006	10000	40010
50024	70153	50016	40016	10000	40010	10000	1851686	535419	50010	40020	10000	70020	10000	40006	10000	40010
50024	70153	50016	40016	10000	40010	10000	1851686	535419	50010	40020	10000	70020	10000	40006	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6], #8
  ldr x0, [x7], #8
  ldr x0, [x8], #8
  ldr x0, [x9], #8
  ldr x0, [x10], #8
  ldr x0, [x11], #8
  ldr x0, [x12], #8
  ldr x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44418	160433	80313	80120	80316	80011	240488	640729	160124	80213	80013	80212	80012	80009	80000	80100
160204	43221	160109	80109	80000	80112	80011	240485	644304	160123	80212	80012	80212	80012	80009	80000	80100
160204	43218	160109	80109	80000	80112	80009	240485	643218	160121	80212	80012	80212	80012	80009	80000	80100
160204	43217	160109	80109	80000	80112	80008	240485	641906	160120	80212	80012	80212	80012	80009	80000	80100
160204	43214	160107	80107	80000	80110	80012	240485	642011	160124	80212	80012	80212	80012	80009	80000	80100
160204	43217	160109	80109	80000	80112	80012	240485	638179	160124	80212	80012	80212	80012	80009	80000	80100
160204	43219	160114	80109	80005	80112	80011	240485	639091	160123	80212	80012	80212	80012	80009	80000	80100
160205	43291	160185	80151	80034	80154	80011	240578	642352	160123	80212	80012	80212	80012	80009	80000	80100
160204	43217	160109	80109	80000	80112	80011	240485	644823	160123	80212	80012	80212	80012	80009	80000	80100
160204	43218	160110	80109	80001	80112	80009	240485	640233	160121	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5408

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44373	160333	80223	80110	80226	80011	240308	645793	160033	80032	80012	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80010	240423	626095	160033	80033	80013	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	632219	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	642158	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	643941	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	644625	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	644252	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	644915	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	647264	160010	80020	80000	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	645371	160010	80020	80000	80020	80000	80001	80000	80010

LDR (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations