Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stxp w0, x1, x2, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 71005 | 34146 | 1003 | 1 | 1002 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 33883 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 33860 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 33863 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 33857 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 33859 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 33876 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 34055 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 34119 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
| 71004 | 34099 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 3000 | 1 | 1000 |
Code:
stxp w0, x1, x2, [x6] add x6, x6, 16
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.5087
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20214 | 26915 | 20560 | 10380 | 10180 | 10379 | 10004 | 35473 | 274714 | 20108 | 10204 | 10004 | 10203 | 30009 | 10004 | 10000 | 10100 |
| 20204 | 25089 | 20101 | 10101 | 10000 | 10102 | 10002 | 35467 | 274300 | 20104 | 10202 | 10002 | 10202 | 30006 | 10003 | 10000 | 10100 |
| 20204 | 25173 | 20103 | 10103 | 10000 | 10102 | 10004 | 35473 | 275535 | 20108 | 10204 | 10004 | 10202 | 30006 | 10003 | 10000 | 10100 |
| 20204 | 25193 | 20103 | 10103 | 10000 | 10104 | 10002 | 35467 | 274852 | 20104 | 10202 | 10002 | 10202 | 30006 | 10001 | 10000 | 10100 |
| 20204 | 25146 | 20103 | 10103 | 10000 | 10102 | 10002 | 35467 | 274599 | 20104 | 10202 | 10002 | 10202 | 30006 | 10003 | 10000 | 10100 |
| 20204 | 25198 | 20101 | 10101 | 10000 | 10102 | 10002 | 35467 | 274847 | 20104 | 10202 | 10002 | 10202 | 30006 | 10003 | 10000 | 10100 |
| 20204 | 25015 | 20103 | 10103 | 10000 | 10102 | 10002 | 35467 | 275296 | 20104 | 10202 | 10002 | 10204 | 30012 | 10003 | 10000 | 10100 |
| 20204 | 25064 | 20103 | 10103 | 10000 | 10102 | 10004 | 35473 | 274183 | 20108 | 10204 | 10004 | 10204 | 30012 | 10003 | 10000 | 10100 |
| 20204 | 25061 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 273675 | 20108 | 10204 | 10004 | 10204 | 30012 | 10003 | 10000 | 10100 |
| 20204 | 25105 | 20103 | 10103 | 10000 | 10102 | 10002 | 35467 | 273465 | 20104 | 10202 | 10002 | 10202 | 30006 | 10003 | 10000 | 10100 |
Result (median cycles for code): 2.5592
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20034 | 26774 | 20467 | 10287 | 10180 | 10288 | 10003 | 35252 | 280955 | 20016 | 10023 | 10003 | 10023 | 30009 | 10004 | 10000 | 10010 |
| 20024 | 25600 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 280746 | 20010 | 10020 | 10000 | 10020 | 30000 | 10001 | 10000 | 10010 |
| 20024 | 25552 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 280346 | 20010 | 10020 | 10000 | 10020 | 30000 | 10001 | 10000 | 10010 |
| 20024 | 25573 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 279996 | 20010 | 10020 | 10000 | 10020 | 30000 | 10001 | 10000 | 10010 |
| 20024 | 25590 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 280081 | 20010 | 10020 | 10000 | 10020 | 30000 | 10001 | 10000 | 10010 |
| 20024 | 25594 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 280088 | 20010 | 10020 | 10000 | 10020 | 30000 | 10001 | 10000 | 10010 |
| 20024 | 25633 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 279891 | 20010 | 10020 | 10000 | 10020 | 30000 | 10001 | 10000 | 10010 |
| 20024 | 25529 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 279310 | 20010 | 10020 | 10000 | 10020 | 30000 | 10001 | 10000 | 10010 |
| 20024 | 25583 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 279575 | 20010 | 10020 | 10000 | 10020 | 30000 | 10001 | 10000 | 10010 |
| 20024 | 25593 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 279833 | 20010 | 10020 | 10000 | 10024 | 30012 | 10003 | 10000 | 10010 |
Code:
stxp w0, x1, x2, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0047
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10205 | 20157 | 10119 | 101 | 10018 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 30144 | 1 | 10000 | 100 |
| 10204 | 30049 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 30012 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 30012 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 30012 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 30012 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10036 | 300 | 532363 | 10136 | 200 | 10050 | 200 | 30012 | 1 | 10000 | 100 |
| 10204 | 30058 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 30012 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 529647 | 10100 | 200 | 10004 | 200 | 30012 | 1 | 10000 | 100 |
| 10204 | 30065 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528873 | 10100 | 200 | 10004 | 200 | 30018 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 30012 | 1 | 10000 | 100 |
Result (median cycles for code): 3.0047
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10025 | 20174 | 10029 | 11 | 10018 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10004 | 20 | 30000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |
| 10025 | 30087 | 10029 | 11 | 10018 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |
| 10024 | 30052 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528963 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |
| 10024 | 30062 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528927 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 30000 | 1 | 10000 | 10 |