Icestorm: LDRSH (post-index, 64-bit) measurements

Code:

  ldrsh x0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1235	2033	1020	1013	1036	1000	20823	17397	2000	1000	1000	1000	1000	1001	1000	1000
2004	1063	2001	1001	1000	1000	1000	21304	17661	2000	1000	1000	1000	1000	1001	1000	1000
2004	1064	2001	1001	1000	1000	1000	21442	17666	2000	1000	1000	1000	1000	1001	1000	1000
2004	1067	2001	1001	1000	1000	1000	21447	17593	2000	1000	1000	1000	1000	1001	1000	1000
2004	1077	2001	1001	1000	1000	1000	21304	17665	2000	1000	1000	1000	1000	1001	1000	1000
2004	1074	2001	1001	1000	1000	1000	21340	17667	2000	1000	1000	1000	1000	1001	1000	1000
2004	1077	2001	1001	1000	1000	1000	21165	18101	2000	1000	1000	1000	1000	1001	1000	1000
2004	1064	2001	1001	1000	1000	1000	21757	17882	2000	1000	1000	1000	1000	1001	1000	1000
2004	1090	2001	1001	1000	1000	1000	21388	17661	2000	1000	1000	1000	1000	1001	1000	1000
2004	1091	2001	1001	1000	1000	1000	21163	17890	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0105

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71301	50161	40156	10005	40247	10002	1850204	534648	50108	40211	10003	70221	10004	40004	10000	40100
50204	70142	50104	40104	10000	40106	10003	1850334	534730	50109	40212	10004	70221	10004	40004	10000	40100
50204	70105	50104	40104	10000	40106	10003	1850280	534712	50109	40212	10004	70289	10013	40015	10000	40100
50204	70107	50104	40104	10000	40106	10003	1850334	534730	50109	40212	10004	70221	10004	40004	10000	40100
50204	70105	50104	40104	10000	40106	10003	1850334	534730	50109	40212	10004	70221	10004	40004	10000	40100
50204	70105	50104	40104	10000	40106	10003	1850334	534730	50109	40212	10004	70221	10004	40004	10000	40100
50204	70105	50104	40104	10000	40106	10003	1850334	534730	50109	40212	10004	70221	10004	40004	10000	40100
50204	70105	50104	40104	10000	40106	10003	1850334	534730	50109	40212	10004	70221	10004	40004	10000	40100
50204	70103	50104	40104	10000	40106	10003	1850334	534730	50109	40212	10004	70221	10004	40004	10000	40100
50204	70105	50104	40104	10000	40106	10003	1850280	534712	50109	40212	10004	70221	10004	40004	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0103

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71282	50070	40065	10005	40156	10003	1850424	535092	50019	40032	10004	70020	10000	40004	10000	40010
50024	70103	50014	40014	10000	40010	10000	1850282	535027	50010	40020	10000	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10000	1850282	535027	50010	40020	10000	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10013	1852273	535625	50063	40073	10015	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10000	1850282	535027	50010	40020	10000	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10000	1850282	535027	50010	40020	10000	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10000	1850363	535054	50010	40020	10000	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10000	1850282	535027	50010	40020	10000	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10000	1850282	535027	50010	40020	10000	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10000	1850282	535027	50010	40020	10000	70020	10000	40004	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsh x0, [x6], #8
  ldrsh x0, [x7], #8
  ldrsh x0, [x8], #8
  ldrsh x0, [x9], #8
  ldrsh x0, [x10], #8
  ldrsh x0, [x11], #8
  ldrsh x0, [x12], #8
  ldrsh x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44261	160428	80313	80115	80316	80011	240613	642243	160124	80213	80013	80212	80012	80009	80000	80100
160204	43229	160109	80109	80000	80112	80012	240529	644121	160124	80212	80012	80212	80012	80009	80000	80100
160204	43227	160109	80109	80000	80112	80011	240529	640688	160123	80212	80012	80212	80012	80009	80000	80100
160204	43223	160109	80109	80000	80112	80012	240529	642572	160124	80212	80012	80212	80012	80009	80000	80100
160204	43225	160109	80109	80000	80112	80010	240714	631561	160122	80212	80012	80252	80052	80049	80000	80100
160204	43244	160109	80109	80000	80112	80011	240653	641210	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160110	80109	80001	80112	80011	240529	644099	160123	80212	80012	80212	80012	80009	80000	80100
160204	43224	160110	80109	80001	80112	80011	240529	639258	160123	80212	80012	80210	80010	80007	80000	80100
160205	43448	160182	80151	80031	80154	80012	240641	641068	160124	80212	80012	80212	80012	80009	80000	80100
160204	43223	160109	80109	80000	80112	80011	240529	644471	160123	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44364	160326	80223	80103	80226	80010	240272	641833	160032	80032	80012	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	642102	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	642123	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	637701	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	638855	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240223	643527	160010	80020	80000	80020	80000	80001	80000	80010
160024	43227	160011	80011	80000	80010	80000	240338	643577	160010	80020	80000	80020	80000	80001	80000	80010
160025	43297	160094	80061	80033	80064	80000	240223	643166	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	646058	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	644960	160010	80020	80000	80020	80000	80001	80000	80010

LDRSH (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations