Icestorm: LDP (pre-index, 32-bit) measurements

Code:

  ldp w0, w1, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
3005	1309	2035	1020	1015	1028	1000	13305	14609	2000	1000	2000	1000	2000	1001	1000	2000
3004	1111	2001	1001	1000	1000	1000	13442	14538	2000	1000	2000	1000	2000	1001	1000	2000
3004	1109	2001	1001	1000	1000	1000	13555	14637	2000	1000	2000	1000	2000	1001	1000	2000
3004	1073	2001	1001	1000	1000	1000	13578	15618	2000	1000	2000	1000	2000	1001	1000	2000
3004	1084	2001	1001	1000	1000	1000	13654	15337	2000	1000	2000	1000	2000	1001	1000	2000
3004	1105	2001	1001	1000	1000	1000	13667	15451	2000	1000	2000	1000	2000	1001	1000	2000
3004	1079	2001	1001	1000	1000	1000	13476	14912	2000	1000	2000	1000	2000	1001	1000	2000
3004	1083	2001	1001	1000	1000	1000	13387	14605	2000	1000	2000	1000	2000	1001	1000	2000
3004	1067	2001	1001	1000	1000	1000	13655	14644	2000	1000	2000	1000	2000	1001	1000	2000
3004	1113	2001	1001	1000	1000	1000	13512	14992	2000	1000	2000	1000	2000	1001	1000	2000

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0178

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60209	71333	50261	40256	10005	40348	10003	1852094	549565	50209	40212	20008	70221	20008	40104	10000	50100
60204	70139	50204	40204	10000	40206	10003	1851391	549361	50209	40212	20008	70221	20008	40104	10000	50100
60204	70141	50204	40204	10000	40206	10003	1851229	549307	50209	40212	20008	70221	20008	40104	10000	50100
60205	70190	50217	40215	10002	40240	10013	1853123	549864	50253	40252	20028	70221	20006	40105	10000	50100
60204	70122	50204	40204	10000	40206	10003	1851150	549224	50209	40212	20008	70221	20008	40104	10000	50100
60204	70117	50204	40204	10000	40206	10013	1852199	549589	50253	40252	20028	70221	20008	40104	10000	50100
60204	70144	50204	40204	10000	40206	10003	1850851	549185	50209	40212	20008	70221	20008	40104	10000	50100
60204	70170	50204	40204	10000	40206	10003	1851202	549302	50209	40212	20008	70221	20008	40104	10000	50100
60204	70119	50204	40204	10000	40206	10003	1850581	549095	50209	40212	20008	70221	20008	40104	10000	50100
60204	70119	50204	40204	10000	40206	10003	1850581	549095	50209	40212	20008	70221	20008	40104	10000	50100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0108

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60029	71222	50079	40074	10005	40166	10003	1850896	549950	50029	40032	20008	70041	20008	40014	10000	50010
60024	70119	50024	40024	10000	40020	10000	1850866	549919	50020	40020	20000	70020	20000	40014	10000	50010
60024	70117	50024	40024	10000	40020	10000	1850731	549874	50020	40020	20000	70020	20000	40014	10000	50010
60024	70118	50024	40024	10000	40020	10000	1850920	549937	50020	40020	20000	70020	20000	40014	10000	50010
60024	70328	50054	40048	10006	40092	10000	1850677	549856	50020	40020	20000	70020	20000	40014	10000	50010
60024	70117	50024	40024	10000	40020	10000	1850812	549901	50020	40020	20000	70020	20000	40014	10000	50010
60024	70128	50024	40024	10000	40020	10000	1851109	550000	50020	40020	20000	70041	20008	40015	10000	50010
60024	70105	50024	40024	10000	40020	10000	1850407	549762	50020	40020	20000	70020	20000	40014	10000	50010
60024	70109	50024	40024	10000	40020	10000	1850353	549744	50020	40020	20000	70020	20000	40014	10000	50010
60024	70105	50024	40024	10000	40020	10000	1850542	549807	50020	40020	20000	70020	20000	40014	10000	50010

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp w0, w1, [x6, #8]!
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0117

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60209	71216	50257	40252	10005	40348	10003	1850501	549038	0	50209	40212	20008	0	70221	20008	40104	10000	50100
60204	70119	50204	40204	10000	40206	10003	1851121	549275	0	50209	40212	20008	0	70221	20008	40104	10000	50100
60204	70113	50204	40204	10000	40206	10003	1850365	549023	0	50209	40212	20008	0	70221	20008	40104	10000	50100
60204	70113	50204	40204	10000	40206	10003	1850419	549041	0	50209	40212	20008	0	70221	20008	40104	10000	50100
60205	70198	50217	40215	10002	40239	10003	1851175	549293	0	50209	40212	20008	0	70363	20050	40127	10000	50100
60204	70131	50204	40204	10000	40206	11279	1529599	468974	1488	47371	38622	19253	14	70221	20008	40104	10000	50100
60204	70158	50204	40204	10000	40206	10003	1850716	549139	0	50209	40212	20008	0	70221	20008	40104	10000	50100
60204	70117	50204	40204	10000	40206	10003	1850527	549077	0	50209	40212	20008	0	70221	20008	40104	10000	50100
60204	70117	50204	40204	10000	40206	10003	1850473	549059	0	50209	40212	20008	0	70221	20008	40104	10000	50100
60204	70117	50204	40204	10000	40206	10003	1850473	549059	0	50209	40212	20008	0	70221	20008	40104	10000	50100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0108

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60030	71363	50093	40086	10007	40200	10003	1850596	549763	50029	40032	20006	70020	20000	40014	10000	50010
60024	70135	50024	40024	10000	40020	10000	1851946	550275	50020	40020	20000	70020	20000	40014	10000	50010
60024	70133	50024	40024	10000	40020	10000	1851352	550077	50020	40020	20000	70020	20000	40014	10000	50010
60024	70134	50024	40024	10000	40020	10000	1851163	550014	50020	40020	20000	70041	20006	40015	10000	50010
60024	70124	50024	40024	10000	40026	10003	1851085	550013	50029	40032	20008	70041	20008	40014	10000	50010
60024	70116	50024	40024	10000	40026	10013	1852600	550489	50072	40072	20028	70041	20008	40014	10000	50010
60024	70162	50024	40024	10000	40026	10003	1851679	550211	50029	40032	20008	70041	20008	40014	10000	50010
60024	70133	50024	40024	10000	40026	10003	1850653	549869	50029	40032	20008	70041	20008	40014	10000	50010
60024	70115	50024	40024	10000	40026	10003	1850653	549869	50029	40032	20008	70041	20008	40014	10000	50010
60024	70115	50024	40024	10000	40026	10003	1850653	549869	50029	40032	20008	70041	20008	40014	10000	50010

Test 4: throughput

Count: 8

Code:

  ldp w0, w1, [x6, #8]!
  ldp w0, w1, [x7, #8]!
  ldp w0, w1, [x8, #8]!
  ldp w0, w1, [x9, #8]!
  ldp w0, w1, [x10, #8]!
  ldp w0, w1, [x11, #8]!
  ldp w0, w1, [x12, #8]!
  ldp w0, w1, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7520

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240209	61197	160334	80240	80094	80241	80008	240461	251243	160116	80208	160016	80235	160073	80033	80000	160100
240204	60127	160111	80106	80005	80108	80008	240469	251259	160116	80208	160016	80208	160016	80006	80000	160100
240204	60128	160111	80106	80005	80108	80008	240461	251223	160116	80208	160016	80208	160016	80006	80000	160100
240204	60127	160111	80106	80005	80108	80008	240461	251229	160116	80208	160016	80235	160070	80033	80000	160100
240204	60121	160111	80106	80005	80108	80008	240467	251349	160116	80208	160016	80208	160016	80006	80000	160100
240204	60130	160111	80106	80005	80108	80008	240459	251198	160116	80208	160016	80208	160016	80006	80000	160100
240204	60126	160111	80106	80005	80108	80008	240462	251202	160116	80208	160016	80208	160016	80006	80000	160100
240204	60128	160111	80106	80005	80108	80008	240461	251208	160116	80208	160016	80208	160016	80006	80000	160100
240204	60128	160111	80106	80005	80108	80008	240461	251153	160116	80208	160016	80208	160016	80006	80000	160100
240204	60125	160111	80106	80005	80108	80008	240461	251176	160116	80208	160016	80208	160016	80006	80000	160100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240029	61193	160239	80149	80090	80151	80008	240205	251328	160026	80028	160016	80020	160000	80001	80000	160010
240024	60097	160011	80011	80000	80010	80000	240178	251328	160010	80020	160000	80020	160000	80001	80000	160010
240024	60087	160011	80011	80000	80010	80036	240516	252200	160082	80056	160072	80020	160000	80001	80000	160010
240024	60082	160011	80011	80000	80010	80000	240181	251300	160010	80020	160000	80020	160000	80001	80000	160010
240025	60177	160063	80037	80026	80037	80000	240187	251198	160010	80020	160000	80020	160000	80001	80000	160010
240024	60084	160011	80011	80000	80010	80000	240181	251357	160010	80020	160000	80020	160000	80001	80000	160010
240024	60085	160011	80011	80000	80010	80000	240181	251327	160010	80020	160000	80020	160000	80001	80000	160010
240024	60084	160011	80011	80000	80010	80000	240181	251323	160010	80020	160000	80020	160000	80001	80000	160010
240024	60087	160011	80011	80000	80010	80000	240178	251359	160010	80020	160000	80020	160000	80001	80000	160010
240024	60084	160011	80011	80000	80010	80000	240181	251348	160010	80020	160000	80020	160000	80001	80000	160010

LDP (pre-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations