Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

B.cc (taken)

Test 1: uops

Code:

  b.ne .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	9771	5675	5675	7779	4125	1375	1384	1004	1
1004	3196	1001	1001	1000	3000	1000	1000	1000	1
1004	2770	1001	1001	1000	3000	1000	1000	1000	1
1004	2836	1001	1001	1000	3000	1000	1000	1000	1
1004	2761	1001	1001	1000	3000	1000	1000	1000	1
1004	2698	1001	1001	1000	3000	1000	1000	1000	1
1004	2683	1001	1001	1000	3000	1000	1000	1000	1
1004	2743	1001	1001	1000	3000	1000	1000	1000	1
1004	2974	1001	1001	1000	3000	1000	1000	1000	1
1004	2776	1001	1001	1000	3000	1000	1000	1000	1

Test 2: throughput

Count: 8

Code:

  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4
  b.ne .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.1544

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	102127	83182	83182	84489	240318	80106	80206	80203	0	0	1	0	0	100
80204	92710	80102	80102	80103	240309	80103	80203	80206	0	0	1	0	0	100
80204	92351	80102	80102	80103	240309	80103	80203	80203	0	0	1	0	0	100
80204	92347	80102	80102	80103	240309	80103	80203	80203	0	0	1	0	0	100
80204	92344	80102	80102	80103	240309	80103	80203	80203	0	0	1	0	0	100
80205	92691	80139	80139	80148	240318	80106	80206	80203	0	0	1	0	0	100
80204	92347	80102	80102	80103	240309	80103	80203	80203	0	0	1	0	0	100
80204	92356	80102	80102	80103	240309	80103	80203	80203	0	0	1	0	0	100
80204	92353	80102	80102	80103	240309	80103	80203	80203	0	0	1	0	0	100
80204	92353	80102	80102	80103	240309	80103	80203	80203	0	0	1	0	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.9602

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80025	366887	115785	115785	128783	240218	80073	80083	80023	1	10
80024	318313	80012	80012	80011	240033	80011	80021	80033	1	10
80024	317735	80012	80012	80011	240033	80011	80021	80021	1	10
80024	317755	80012	80012	80011	240033	80011	80021	80029	1	10
80024	316056	80012	80012	80011	240033	80011	80021	80027	1	10
80024	316680	80012	80012	80011	240033	80011	80021	80029	1	10
80024	316520	80012	80012	80011	240033	80011	80021	80021	1	10
80024	316588	80012	80012	80011	240033	80011	80021	80031	1	10
80024	316606	80012	80012	80011	240033	80011	80021	80021	1	10
80024	316610	80012	80012	80011	240033	80011	80021	80021	1	10