Icestorm: LDRSB (unsigned offset, 32-bit) measurements

Code:

  ldrsb w0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	652	1021	1	1020	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	10001	30130	10003	1859587	694038	0	40106	30212	10004	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1859980	694182	0	40150	30247	10017	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859662	694094	0	40106	30212	10004	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	10004	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70159	40018	30017	10001	30040	10000	1859469	694619	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10015	1859881	694805	40060	30071	10017	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40025	70148	40021	30019	10002	30042	10000	1859625	694708	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010

Test 3: throughput

Count: 8

Code:

  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]
  ldrsb w0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40176	80129	101	80028	100	80008	300	248190	80108	200	80012	200	80012	1	80000	100
80204	40058	80105	101	80004	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40061	80101	101	80000	100	80008	300	640412	80108	200	80012	200	80072	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640196	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40348	80035	11	80024	10	80008	30	400604	80018	20	80012	20	80000	1	80000	10
80024	40073	80011	11	80000	10	80000	30	642578	80010	20	80000	20	80000	1	80000	10
80024	40078	80011	11	80000	10	80000	30	640346	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80057	30	385623	80067	20	80069	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10

LDRSB (unsigned offset, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations