Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDHN2 (vector, 4S)

Test 1: uops

Code:

  addhn2 v0.8h, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372300612548251000100010003983130301830373037241532895100010003000303730371110011000073216112630100030383038303830383038
100430372300612548251000100010003983131301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372300612548251000100010003983131301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
1004303723001562548251008100010003983131301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372300612548251000100010003983131301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372300612548251000100010003983131301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372200612548251000100010003983131301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372300612548251000100010003983130301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
10043037233660612548251000100010003983131301830373037241532895100010003000303730371110011000073116112630100030383038303830383038
100430372200612548251000100010003983131302230373037241532895100010003000303730371110011000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  addhn2 v0.8h, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372259006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010002710121622296340100001003003830038300383003830038
10204300372252550072629548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
10204300372259006129548251010010010000100100005004277313030054030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
102043003722518006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000710131622296340100001003003830038300383003830038
1020430037225150053629548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
102043003722524006129548251010010010000100100005004277313130018030037300372826532874510100200100002003049230037300371110201100991001001000010000710121622296340100001003003830038300383003830038
1020430037225180025129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000712121622296340100001003003830038300383003830038
102043003722530072629548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
1020430037225435006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
102043003722572006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)090e181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000015629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216232963010000103003830038300383003830038
10024300372250000372629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316222963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250100044129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000640216232963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216322963010000103003830038300383003830038
10024300372250000072629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225000096129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640316322963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216322963010000103003830038300383003830038
10024300372250000156129548251001010100001010000504277313030018300373003728287328767100102010000203000030078300371110021109101010000100000640316222963010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216232963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  addhn2 v0.8h, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225061295482510100100100001001000050042773133001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018330037300372826502728745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250557295482510100100100001001000050042773133001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250124295482510100100100001001000050042773133001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037232061295482510100100100001001000050042773133001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773133001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731330018030037300372826502628745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250645295482510100100100001001000050042773133001803003730037282650328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000000006403162229630010000103003830038300383003830038
1002430037225000000006129548251001710100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000303006402162229630010000103003830038300383003830038
10024300372250000000076029548251001811100081010000504277313300183003730037282870728786100102010000203000030037300371110021109101010000100000003006402162229630010000103003830038300383003830038
100243003722501000013506129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000100006402162229630010000103003830038300383003830038
1002430037225000000006129548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000000006402162229630010000103003830038300383003830038
1002430085225000100006129548251001010100001010000504277313300183003730037282870328767101612010162203000030037301312110021109101010000100000003006402322229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  addhn2 v0.8h, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000300612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250000375880612954825101001001000010010149500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500001200942954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500003900612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002023000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500001800612954825101001001000810010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000484407101161129634100001003003830038300383003830038
102043003722500001200612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500000001682954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001030306402162229630010000103003830038300383003830038
1002430037224000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000103015906402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010108106402162229630010000103003830038300383003830038
1002430037225000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100012006402162229630010000103003830038300383003830038
1002430037225000001032954825100101010000101000050427731313012630037300372828732876710010201000020300003003730037111002110910101000010009606402162229630010000103003830038300853003830038
10024300372250001156822953925100101010008101000050427731313001830085300372829032876710010201000020300003003730037111002110910101000010108106402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010007806402162229630010000103003830038300383003830038
10024300372240000122512954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010008106402162229630010000103003830038300383003830038
1002430037225000021208295482510010101000010101495042773131300183003730037282873287671001020100002030000300373003711100211091010100001070016402162229630010000103003830038300383003830038
100243003722500000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010420306402162229630010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  addhn2 v0.8h, v8.4s, v9.4s
  movi v1.16b, 0
  addhn2 v1.8h, v8.4s, v9.4s
  movi v2.16b, 0
  addhn2 v2.8h, v8.4s, v9.4s
  movi v3.16b, 0
  addhn2 v3.8h, v8.4s, v9.4s
  movi v4.16b, 0
  addhn2 v4.8h, v8.4s, v9.4s
  movi v5.16b, 0
  addhn2 v5.8h, v8.4s, v9.4s
  movi v6.16b, 0
  addhn2 v6.8h, v8.4s, v9.4s
  movi v7.16b, 0
  addhn2 v7.8h, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk data (08)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200651510000392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000010115116112006101600001002006520065200652006520065
160204200641510000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010113216212006101600001002006520065200652006520065
160204200641500000392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010113216222006101600001002006520065200652006520065
160204200641500000622580100100800001008000050064000002004520064200643228010020080000200240000203062006411160201100991001001600001000010112116212006101600001002006520065200652006520065
160204200641500000392580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000010116116322006101600001002006520065200652006520065
160204200641500000602580100100800001008000061464000002004520064200643228010020080000200240000200642006411160201100991001001600001000010112116122006101600001002006520065200652006520065
1602042006415100001252580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000010111116122006101600001002006520065200652006520065
160204200641500000602580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000310112216212006101600001002006520065200652006520065
160204200641500000622580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000010112216212006101600001002006520065200652006520065
160204200641500000622580100100800001008000050064000002004520064200643228010020080000200240000200642006411160201100991001001600001000010116216332006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242008715000045278001212800001280000626400001152003220051200513228001220800002024000020051200511116002110910101600001000101248311525211814200482201160000102005220052200522005220052
1600242005115000071027800121280000128000062640000115200322005120051322800122080000202400002005120051111600211091010160000100010117841525211149200482201160000102005220052200522005220052
1600242005115000068278001212800001280000626400001152003220051200513228001220800002024000020051200511116002110910101600001000101078411425211814200482201160000102005220052200522005220052
16002420051150000452780012128000012800006264000011520032200512005132280012208000020240000200512005111160021109101016000010001010684172521189200482201160000102005220061200522005220052
16002420051150000452780012128000012800006264000011520032200512005132280012208000020240000203732005111160021109101016000010001010884163421188200572201160000102005220052200522005220052
160024200511500004527800121280000128000062640000115200322005120051322800122080000202400002005120051111600211091010160000100010109114162521167200482201160000102005220052200522005220052
1600242005115000045278001212800001280000626400001152003220051200513228001220800002024000020051200511116002110910101600001000101051141102521157200482201160000102005220052200522005220052
1600242005115100053027800121280000128000062640000115200322005120051322800122080000202400002005120051111600211091010160000100010105841725211149200482201160000102005220052200522005220052
16002420051150000452780012128000012800006264000011520032200512005132280012208000020240000200512006011160021109101016000010001010584182521157200482201160000102005220052200522005220052
16002420051150000452780012128000012800006264000011520032200512005132280012208000020240000200512037311160021109101016000010001009884152521177200482201160000102005220052200522005220052

Test 6: throughput

Count: 16

Code:

  addhn2 v0.8h, v16.4s, v17.4s
  addhn2 v1.8h, v16.4s, v17.4s
  addhn2 v2.8h, v16.4s, v17.4s
  addhn2 v3.8h, v16.4s, v17.4s
  addhn2 v4.8h, v16.4s, v17.4s
  addhn2 v5.8h, v16.4s, v17.4s
  addhn2 v6.8h, v16.4s, v17.4s
  addhn2 v7.8h, v16.4s, v17.4s
  addhn2 v8.8h, v16.4s, v17.4s
  addhn2 v9.8h, v16.4s, v17.4s
  addhn2 v10.8h, v16.4s, v17.4s
  addhn2 v11.8h, v16.4s, v17.4s
  addhn2 v12.8h, v16.4s, v17.4s
  addhn2 v13.8h, v16.4s, v17.4s
  addhn2 v14.8h, v16.4s, v17.4s
  addhn2 v15.8h, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044009330001741251601001001600171001600005001280000004002004003940048199733200061601002001600002004800004004840039111602011009910010016000010000000101100111611400361600001004004040050400404004040040
160204400393000041251601001001600001001600005002438865154002004004840048199733200061601002001600002004800004003940039111602011009910010016000010000000101100011611400361600001004004040040400404004040040
1602044003930000706251601171001600001001600005001280000004002004004840039199733199971601002001600002004800004003940049111602011009910010016000010000000101100011611400451600001004005040040400524004040040
160204400392990041251601001001600001001600005001280000004002904003940039199733199971601002001600002004800004003940039111602011009910010016000010000000101100111611400361600001004004040040400494004040040
16020440049300018412516011710016000010016000050012800000040020040039400481997331999716010020016000020048000040039400391116020110099100100160000100003500101100011611400361600001004004040040400404004040050
160204400393000041251601171001600001001600005001280000004002004003940048199733199971601002001600002004800004003940039111602011009910010016000010000000101100011611400361600001004005040040400404004940049
160204400393000041251601001001600011001600005001280000004002004003940039199733199971601002001600002004800004004840039111602011009910010016000010000200101100111611400361600001004005040040400404004040040
160204400393000041251601001001600001001600005001280000004003004003940049199733199971601002001600002004800004003940039111602011009910010016000010000000101100011611400361600001004004040040400414004040040
160204400392990041251601001001600171001600005001280000004002004003940039199733199971601002001600002004800004003940039111602011009910010016000010000000101100011611400361600001004004040050400404004040040
160204400483000041251601001001600171001600005001280000004002904003940039199733199971601002001600002004800004004940039111602011009910010016000010000100101350111611400361600001004004940040400494004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400563000055251600101016000010160000501280000114002040039400391999632001916001020160000204800004003940039111600211091010160000105201002231118162111614400462012160000104029140120400404004040040
1600244003929900462516002710160000101600005012800001140021400394003919996320019160010201600002048000040039400391116002110910101600001000100223111516211151540036207160000104004040040400404004040040
160024400393001518562516001010160000101600005023989991140020400394003919996320019160010201600002048000040039400391116002110910101600001000100243121616211151540045206160000104004040040400404004040040
16002440039300007112516001010160000101600005012800001040020400494004919996320019160010201600002048000040039400391116002110910101600001000100243121716211171740036206160000104005040040400404004040040
16002440048299005225160010101600001016000050128000011400204003940039199963200191600102016000020480000400394003911160021109101016000010001002431216162121610400362012160000104004140040400404004040050
1600244003929900622516001010160000101600005012800001040020400394004819996320019160010201600002048000040039400391116002110910101600001010100223211716221151640045206160000104005040050400404004040050
1600244003930000462516002810160017101600005012800001140020400394003919996320028160010201600002048000040039400391116002110910101600001000100223521516221161440036209160000104006040049400504004040040
1600244003930000163251600101016001710160000501280000104002040039400391999632001916001020160000204800004003940039111600211091010160000103010022321151622116940036406160000104005040040400404004040040
160024400393000052251600101016000010160000501280000014002140039400391999632001916001020160000204800004003940039111600211091010160000100010024319117162221717400364012160000104004040040400404004040040
1600244003930000522516001010160000101600005012800000140020400394003919996320019160010201600002048000040039400391116002110910101600001000100246221616222161640045406160000104004040049400494004040040