Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDHN (vector, 2D)

Test 1: uops

Code:

  addhn v0.2s, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723606125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723906125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037231206125482510001000100039831303018303730372415328951000100020003037303711100110001073116112630100030383038303830383038
1004303723306125482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  addhn v0.2s, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225015629548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722406129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225044129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225025129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722410000000612954825100101010000101000060427731303001830037300372828732876710012201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722510000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000000942954825100101010000101000050427731303001830037300372828732876710012201000020200003003730037111002110910101000010000003006402162229630010000103003830038300383003830038
100243003722500000000622954825100121210000121000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229632210000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
100243003722500000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000003006402162229630010000103003830038300383003830038
100243003722410000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  addhn v0.2s, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722400000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722400000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722500000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038
102043003722400300612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071001161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000006406162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000306402162229630010000103003830038300383003830038
10024300372250053629548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250010329548251001010100001010000504281384300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
10024300372250061295481011001010100001010000504277313300183003730037282873287671001020104912020000300373003711100211091010100001000006403162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001003006402162229630010000103003830038300383003830038
10024300372240126129548251001010100001010000504280027300183003730037282873287671001020100002020000300373003711100211091010100001000306402162229630010000103003830038300383003830038
1002430037225006129548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722521210329548251001010100001010000504277313300183003730037282873287671001020100002020000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  addhn v0.2s, v8.2d, v9.2d
  addhn v1.2s, v8.2d, v9.2d
  addhn v2.2s, v8.2d, v9.2d
  addhn v3.2s, v8.2d, v9.2d
  addhn v4.2s, v8.2d, v9.2d
  addhn v5.2s, v8.2d, v9.2d
  addhn v6.2s, v8.2d, v9.2d
  addhn v7.2s, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150003025801081008000811980020500640132120020200392003999776999080120200800322001600642003920039118020110099100100800001001311151181160220100800001002004020040200402004020040
8020420039150003025801081008000810080020500640132120020200392003999776999080120200800322001600642003920039118020110099100100800001001011151180160020036800001002004020040200402004020040
80204200391500023125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001002300051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080212500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001002000051101161120036800001002004020040200402004020040
8020420039150004125801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040
8020420039150008325801001008000010080000500640000120020200392003999733999780100200800002001600002003920039118020110099100100800001000000051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010205020151615122003680000102004020040200402004020040
800242003915004563800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010105020115016162003680000102004020040200402004020040
800242003915004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010105020111610152003680000102004020040200402004020040
800242003915004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010105020131614122003680000102004020040200402004020040
800242003915004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010135020131616172003680000102004020040200402004020040
800242003915004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010105020121615112003680000102004020040200402004020040
800242003915004025803991080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010135020161616132003680000102004020040200402004020040
80024200391500325258001010800001080000506400000020020200392003999963100198001020800002016000020039200391180021109101080000102935020161615152003680000102004020040200402004020040
800242003915004025800101080000108000050640000002002020039200399996310019800102080000201600002003920039118002110910108000010105020131712102003680000102004020040200402004020040
800242003915004025800101080000108000050640000112002020039200399996310019800102080000201600002003920039118002110910108000010005020111616132003680000102004020040200402004020040