Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDV (16B)

Test 1: uops

Code:

  addv b0, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037222106125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037226606125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
1004303722006125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
1004303723606125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
1004303722006125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100020003037303711100110001073116112629100030383038303830383038
10043037231206125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
10043037230022925472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038
1004303723006125472510001000100039816003018303730372414328951000100020003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  addv b0, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722506129547251010010010000100100005004277160030018030037300372826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160030018030037300372826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722406129547251010010010000100100005004277160030018030037300372826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160130018030084300372826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722406129547251010010010000100100005004277160130018030037300372826482874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160130018030037300372826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160130018030037300372826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722506129547251010010010000100100005004277160130018030037300372826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722406129547251010010010000100100005004277160130018030037300372826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003722406129547251010010010000100100005004277160030018030037300852826432874510100200100002002000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722506129547251001010100001010000504277160030018300843003728286328767100102010000202000030037300371110021109101010000100000640316222962910000103003830038300383003830038
100243003722506129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722506129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722506129547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100000640216122962910000103003830038300383003830038
1002430037225072629547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100100640216222962910000103003830038300383003830038
1002430037225377529547251001010100001010000504277160130018300373003728286328767100102010000202000030037300371110021109101010000100028780661216222962910000103003830038300383003830038
1002430037225053629547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225010329547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100130640216222962910000103003830038300383003830069
100243003722506129547251001010100001010000604277160030054300373003728290328767100102010000202000030037300372110021109101010000100004640232242962910000103003830038300383003830038
100243003722506129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  addv b0, v8.16b
  addv b1, v8.16b
  addv b2, v8.16b
  addv b3, v8.16b
  addv b4, v8.16b
  addv b5, v8.16b
  addv b6, v8.16b
  addv b7, v8.16b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420125151011121561163025801081008000810080020500640132020020200392003999776100168012020080032200160064201162010611802011009910010080000100022001115118116220036800001002004020040200402004020040
802042003915000000150302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013212002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013212002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040
802042003915000000006952580108100800081008002050064013212002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040
80204200391500000000302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000001115118016020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)d9dbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500402580010108000010800005064000002002002003920039999631001980010208000020160000200392003911800211091010800001003502006160075200360080000102004020040200402004020040
80024200391500402580010108000010800005064000012002002003920039999631001980010208000020160000200392003911800211091010800001000502007160075200360080000102004020040200402004020040
80024200391500402580010108000010800005064000002002002003920039999631001980010208000020160000200392003911800211091010800001006502007160057200360080000102004020040200402004020040
80024200391500402580010108000010800005064000002002002003920039999631001980010208000020160000200392003911800211091010800001000502007160075200360080000102004020040200402004020040
800242003915004025800101080000108000050640000120020020039200399996310019800102080000201600002003920039118002110910108000010012502007160057200360080000102004020040200402004020040
80024200391500402580010108000010800005064000002002002003920039999631001980010208000020160000200392003911800211091010800001000502005160075200360080000102004020040200402004020040
80024200391500402580010108000010800005064000002002002003920039999631001980010208000020160000200392003911800211091010800001000502005160057200360080000102004020040200402004020040
8002420039150040258001010800001080000506400000200200200392003999963100198001020800002016000020039200391180021109101080000100111502005160075200360080000102004020040200402004020040
800242003915004025800101080000108000050640000020020020039200399996310019800102080000201600002003920039118002110910108000010005020071620572003620080000102004020040200402004020040
80024200391500402580010108000010800005064000002002002003920039999631001980010208000020160000200392003911800211091010800001000502005160057200360080000102004020040200402004020040