Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDV (8H)

Test 1: uops

Code:

  addv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372200000000612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
1004303723000000002232547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
100430372200000600612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
100430372200000000612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
100430372300000000612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
100430372200000600612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
100430372300000300612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
100430372300000000612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
100430372300000000612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038
100430372200000000612547251000100010003981600301830373037241432895100010002000303730371110011000000000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  addv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372240000014929547251010010010000100100005004277160030018300373003728264328745101002001000020020000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
10204300372250000056329547251010010010000100100005004277160130018300373003728264328745101002001000020020000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728264328745101002001000020020000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
1020430037225000008429547251010010010000100100005004277160130018300373003728264328745101002001000020020000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
1020430037225000008229547251010010010000100100005004277160030018300373003728264328745101002001000020020000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728264328745101002001018220020000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
10204300372250000012429547251010010010000100100005004277160030018300373003728264328745101002001000020020000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
10204300372240000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000517101161129633100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277160030018300373003728264328745101002001000020020000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
1020430037225000006129547251010010010000100100005004277363130018300373003728264328745101002001000020020000300373003711102011009910010010000100037101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250014529547251001010100001010000504277160130018030037300372828632876710010201000020200003003730037111002110910101000010000640716232962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020200003003730037111002110910101000010000640216232962910000103003830038300383003830038
10024300372250059329547251001010100001010000504277160130018030037300372828632876710010201000020200003003730037111002110910101000010100640216232962910000103003830038300383003830038
1002430037225006129547251001010100071010000504277160130018030037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010148504277160130018030037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020200003003730037111002110910101000010190640216222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020200003003730037111002110910101000010000640216232962910000103003830038300383003830038
10024300372250017029547251001010100001010000504278512130018030037300372828632876710010201000020200003003730037111002110910101000010000640216232962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018030037300372828632876710010201000020200003003730037111002110910101000010000640216232962910000103003830038300383003830038
1002430037225606129547251001010100001010000504277160130018030037300372828632876710010201000020200003003730037111002110910101000010000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  addv h0, v8.8h
  addv h1, v8.8h
  addv h2, v8.8h
  addv h3, v8.8h
  addv h4, v8.8h
  addv h5, v8.8h
  addv h6, v8.8h
  addv h7, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915072258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118116020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
802042003915072258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
802042003915081258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
80204201381503025801081008000810080020500640132200202003920039997769990801202008003220016006420039200391180201100991001008000010019401115118016020036800001002004020040200402004020040
802042003915072258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
802042003915030258010810080008100800205006401322002020039200399977699908012020080032200160064200392003911802011009910010080000100001115118016120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150001032580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502000216000112003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502000116000112003680000102004020040200402004020040
800242009315000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502000116000112003680000102004020040200402004020040
800242003915006822580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502000116010112003680000102004020040200402004020040
8002420039150002512580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502000116010112003680000102004020040200402004020040
800242003915000402580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010100502001116020112003680000102004020040200402004020040
8002420091150104182580010108000010800005064000012006820039200399996310019800102080000201600002003920039118002110910108000010000502000116010112003680000102004020040200402004020040
800242003915000822580010108000010800005064016412002020039200399996310019800102080000201600002003920039118002110910108000010000502000116000112003680000102004020040200402004020040
800242003915000822580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010130502000116000112003680000102004020040200402004020040
8002420039150001052580010108000010800005064000012002020039200399996310019800102080000201600002003920039118002110910108000010000502000116010112003680000102004020040200402024920040