Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADD (vector, 2S)

Test 1: uops

Code:

  add v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715008216872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716006116872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716006116872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037161912716872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716006116872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  add v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000084196872510100100100001001000050028476800200182003720037184223187441010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000003971021622197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187441012520010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
102042003715000061196872510100100100001001000062628476800200182003720037184223187451012520010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
102042003715000061196762510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000002071021622197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000004071021622197910100001002003820038200382003820038
102042003715000061196872510125125100001001000062628476801200182003720037184223187441010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071021622197910100001002003820038200382003820038
1020420037150030611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000005771021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010021640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001023640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640016331978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010060640316331978510000102003820038200382013220038
100242003715006119676441001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000104521640316331978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010060640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001013640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820228200382003820038

Test 3: Latency 1->3

Code:

  add v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382018020038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451025620010500200200002003720037111020110099100100100001001327101161119791100001002003820038200382003820038
1020420037150061196874310100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007507101161119791100001002003820038200382003820038
102042003715096611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010006307101161119791100001002003820038200382003820038
10204200371500331196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150474196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001013640216221978510000102003820038200382003820038
100242003715161196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150145196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037150245196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
1002420037157124196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371501109196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001013640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  add v0.2s, v8.2s, v9.2s
  add v1.2s, v8.2s, v9.2s
  add v2.2s, v8.2s, v9.2s
  add v3.2s, v8.2s, v9.2s
  add v4.2s, v8.2s, v9.2s
  add v5.2s, v8.2s, v9.2s
  add v6.2s, v8.2s, v9.2s
  add v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420047150000241258010010080000100800006386400001200192008820038997339996801002008000020016000020038200381180201100991001008000010010051146161111200350800001002003920039200392003920039
80204200381500033241258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051141016611200350800001002003920039200392003920039
80204200381500002852580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000511410161111200350800001002003920039201002003920039
80204200881500002412580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100100511410161010200350800001002003920039200392003920039
8020420038150000241258010010080000112800965006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051148161111200350800001002003920039200392003920039
802042003815000024125801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000005114516811200350800001002003920039200392003920039
802042003815000022062580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100130511410161010200350800001002003920039200392003920039
8020420038150000220925801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000305114101688200350800001002003920039200392003920039
80204200381500002412580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000511410161110200350800001002003920039200902003920039
802042003815000028325801001008000010080000500640000120019200382003899731199968010020080098200160000200892003811802011009910010080000100002511411321010200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715098325800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010105020151613112003500080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010005020161614142003500080000102003920039200392003920039
8002420038150010225800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010205020161615152003500080000102003920039200392003920039
8002420038150016725800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010005020131617122003500080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010105020161611152003500080000102003920039200392003920039
800242003815006025800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010005020151615152003500080000102003920039200392003920039
800242003815008125800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010005020161613132003500080000102003920039200392003920039
8002420038150035625800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010105020151612122003500080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010105020161617132003500080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899960310018800102080000201600002003820038118002110910108000010005020171611162003500080000102003920039200392003920039