Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADD (vector, 4H)

Test 1: uops

Code:

  add v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150456116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160156116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715066116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  add v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000145196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000003007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001015050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715089196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150103196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  add v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000124196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000103196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001251000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010047101161119791100001002003820038200862013420038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000145196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002033020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000900103196872510010101000010100005028476800200182003720037184443187671016320100002020000200372003741100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420085150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219788010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000000198196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001044000006402162219785010000102003820038200382003820038
10024200371500000000231196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005528476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  add v0.4h, v8.4h, v9.4h
  add v1.4h, v8.4h, v9.4h
  add v2.4h, v8.4h, v9.4h
  add v3.4h, v8.4h, v9.4h
  add v4.4h, v8.4h, v9.4h
  add v5.4h, v8.4h, v9.4h
  add v6.4h, v8.4h, v9.4h
  add v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)193f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591511040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511021611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
802042003815000402580125100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100005110116112003525800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010010511011611200350800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100005110116112003525800001002003920039200392003920039
8020420038150001452580100100800001008000050064000002001920038200389973399968012520080000200160000200382003811802011009910010080000100005110116112003525800001002003920039200392003920039
802042003815000103258010010080000100800005006400000200192003820038997339996801252008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
80204200381500040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011631200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004015000003925800101080000108000050640000120019020038200389996310018800102080000201600002008920038118002110910108000010000050204164420035080000102003920039200392003920039
800242003815000003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050204167620035080000102003920039200392003920039
800242003815000003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050204164320035080000102003920039200392003920039
800242003815000003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050203164320035080000102003920039200392003920039
800242003815000003925800101080076108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050206164320035080000102003920039200392003920039
800242003815000003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050204164320035080000102003920039200392003920039
800242003815000003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050203164420035080000102003920039200392003920039
80024200381500018306025800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050207167720035080000102003920039200392003920039
800242003815000003925800101080080108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050204167720035080000102003920039200392003920039
800242003815000003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000050206166720035080000102003920039200392003920039