Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADD (vector, 4S)

Test 1: uops

Code:

  add v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716061168725100010001000264680020182037203715723189510001000200020372037111001100073216111787100020382038203820382038
1004203716061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203716061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150103168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725101210001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
1004203715061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  add v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371550170196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500170196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500105196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038201362003820038
10204200371500315196872510100100100001001000050028476800200182003720037184223187451010020010000202200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
1020420037150082196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382008620038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371503022219687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382018020038
1002420037150010319687251001010100001010000502848963200182003720037184440318767100102010000202000020037200372110021109101010000100000006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150069119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000026402163219785310000102003820038200382003820038
100242003715006119687251001010100001010000502847680200182003720037184440318767100102010335202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680200542003720084184477318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  add v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000170196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200542003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000147196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150110000026819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006441016121219785010000102003820038200382003820038
1002420037150110000026819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006441016111019785010000102003820038200382003820038
1002420037150110000026819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006441016101019785010000102003820038200382003820038
1002420037150110000026819687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006441016101019785010000102003820038200382003820038
10024200371501100000211019687251001010100001010000502847680120018200372008418448318767100102010000202000020037200371110021109101010000100000006441016101019785010000102003820038200382003820038
10024200371501100000215419687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006441016101019785010000102003820038200382003820038
1002420037150110000026381968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000644101610519785010000102003820038200382008520038
10024200371501100000275019687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006441016101019785010000102003820038200382003820038
100242003715011000002681968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000644101651319785010000102003820038200382003820038
100242003715011000002681968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000644111651019785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  add v0.4s, v8.4s, v9.4s
  add v1.4s, v8.4s, v9.4s
  add v2.4s, v8.4s, v9.4s
  add v3.4s, v8.4s, v9.4s
  add v4.4s, v8.4s, v9.4s
  add v5.4s, v8.4s, v9.4s
  add v6.4s, v8.4s, v9.4s
  add v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006715000001452580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051102161120035800001002003920039200392003920039
802042003814900001202580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
802042003814900001242580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381550000402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500000822580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500000402580100100800001008011250064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381560000402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050201116131020035080000102003920039200392003920039
800242003815000003925800101080000108000050640000120019200382003899967100188001020800002016000020038200381180021109101080000100005020141612920035080000102003920039200392003920039
80024200381500000230258001010800001080000506400001200192003820038999631001880010208009720160000200382003811800211091010800001000050201116171220035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631010180118208000020160000200382003811800211091010800001000050201116141720035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050201516122120035080000102003920039200392003920039
8002420038150000060258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050201216161320035080000102003920039200392003920039
8002420038150000039258001010800001080097506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050201316151220035380000102003920039200392003920039
8002420038150000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001010050201316111120035080000102003920039200392003920039
80024200381500000363258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050201216131620035080000102003920039200392003920039
8002420038150000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050201116141420035080000102003920039200392003920039