Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADD (vector, 8B)

Test 1: uops

Code:

  add v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110002073216111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042085150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  add v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
1020420037150023619687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042008415006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150381611968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640416221978510000102003820038200382003820038
100242003715039611968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018020037200371844403187671001022100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715012611968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715007261968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715012611968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715012611968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500821968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768020018020037200371844403187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  add v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371505250611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150150611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150210611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150001031968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150120611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371505070611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000901031968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000020006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000060611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000300611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001004000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001832003720037184443187671001020100002020000200372003711100211091010100001000000006404162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000002580611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000000006405162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
100242003715000004050611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  add v0.8b, v8.8b, v9.8b
  add v1.8b, v8.8b, v9.8b
  add v2.8b, v8.8b, v9.8b
  add v3.8b, v8.8b, v9.8b
  add v4.8b, v8.8b, v9.8b
  add v5.8b, v8.8b, v9.8b
  add v6.8b, v8.8b, v9.8b
  add v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042004915003604025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010002051102161120035800001002003920039200392003920039
80204200381550004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051102161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815000034825801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020281625272003580000102003920039200392003920039
80024200381500000392580010108000012800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020141627272003580000102003920039200392003920039
80024200381500000392580010108000012800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010005020281615282003580000102003920039200392003920039
8002420038150000153925800101080000128000050640000020019200382003899963100188001020800002016000020038200381180021109101080000106605020161628292003580000102003920039200392003920039
80024200381500000392580010108000012800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020261629282003580000102003920039200392003920039
80024200381500000392580010108000012800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020281630142003580000102003920039200392003920039
800242003815000103925800101080000128000050640000020019200382003899963100188001020800002016000020038200381180021109101080000105705020291628282003580000102003920039200392003920039
80024200381500000392580010108000012800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010605020281616282003580000102003920039200392003920039
800242003815000015392580010108000012800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020281630302003580000102003920039200392003920039
80024200381500000392580010108000012800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010605020151628292003580000102003920039200392003920039