Firestorm: AESD measurements

Code:

  aesd v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	3	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	3	73	1	16	1	1	2630	1000	3038	3038	3038	3084	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	1	132	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  aesd v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	768	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	124	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	631	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	643	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	480	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	346	29548	25	10100	110	10024	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	394	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	124	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	292	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	223	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	232	0	0	0	0	0	9	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10160	20	10000	20	20000	30037	30084	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	661	2	16	4	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	945	29548	25	10010	10	10000	10	10000	50	4278670	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	1913	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	12	28767	10012	20	10000	20	20336	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	264	0	0	554	29548	25	10010	10	10000	10	10000	50	4277313	30018	30084	30037	28287	3	28862	10010	20	10166	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	2	0	661	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	264	0	0	145	29548	25	10028	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30132	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	532	29548	25	10010	10	10008	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	2	0	0	0	640	2	16	2	4	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	6	0	0	569	29548	25	10010	10	10000	10	10000	50	4277313	30018	30084	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	2	0	661	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30133
10024	30037	232	0	0	0	0	0	0	0	0	124	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	1	0	124	0	810	29548	25	10010	10	10000	10	10000	50	4277313	30018	30133	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	15	0	0	106	29548	25	10010	10	10008	17	10000	50	4278670	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30086	30038	30038	30038

Test 3: Latency 1->2

Code:

  aesd v0.16b, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	0	0	0	0	61	29528	25	10100	100	10000	104	10000	533	4277160	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	0	3	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	1	821	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30070	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	0	2	24	2	2	29629	1	10000	100	30038	30038	30085	30086	30038
10204	30037	233	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10150	522	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	0	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	1	0	0	132	0	1	97	29547	25	10100	104	10000	100	10000	500	4277160	30090	30037	30037	28252	6	28789	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	2	1	1	1	722	0	2	24	2	2	29700	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	1	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20466	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	0	2	56	3	2	29629	0	10000	100	30038	30038	30038	30134	30038
10204	30037	234	0	0	0	0	0	0	1	139	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28733	10100	200	10165	204	20000	30132	30132	4	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	0	0	1	1	1	718	0	0	40	0	0	29645	1	10000	100	30038	30038	30038	30134	30038
10204	30037	233	0	0	0	0	21	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	10	28733	10100	200	10167	200	20000	30037	30037	2	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	0	2	24	2	2	29629	0	10000	100	30038	30086	30038	30038	30132
10204	30037	233	0	0	0	0	0	0	1	97	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30074	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	3	0	1	1	1	722	0	2	24	2	2	29702	0	10000	100	30038	30038	30038	30229	30038
10204	30037	233	0	0	0	0	564	0	1	97	29547	25	10100	100	10000	100	10000	511	4277160	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	1	1	1	722	0	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	3	0	0	0	1	139	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28252	6	28753	10100	210	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	10956	0	1	1	1	769	0	2	32	2	2	29629	0	10000	100	30038	30038	30038	30086	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	233	1	0	1	0	0	0	0	0	2	258	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10160	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	5510	0	644	10	16	10	11	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	234	1	0	1	0	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28290	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	10	16	10	10	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	1	0	1	1	0	0	0	0	2	68	29547	25	10010	10	10008	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	0	0	0	644	11	16	10	10	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	241	1	0	1	0	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30054	30037	30037	28286	3	28767	10160	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	8	32	10	11	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	1	0	1	0	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28805	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	2	0	0	0	0	0	644	11	16	10	11	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	232	1	0	1	0	0	0	0	88	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	11	16	5	10	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	232	1	0	1	0	0	0	276	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	665	10	16	10	10	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	1	0	1	0	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30084	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	10	16	12	10	29629	10000	10	30038	30132	30038	30038	30038
10024	30037	233	1	0	1	0	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30090	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	11	16	16	10	29667	10000	10	30038	30038	30038	30038	30038
10024	30037	233	1	0	1	0	0	0	0	0	2	68	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	644	10	16	5	10	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  aesd v0.16b, v8.16b
  movi v1.16b, 0
  aesd v1.16b, v8.16b
  movi v2.16b, 0
  aesd v2.16b, v8.16b
  movi v3.16b, 0
  aesd v3.16b, v8.16b
  movi v4.16b, 0
  aesd v4.16b, v8.16b
  movi v5.16b, 0
  aesd v5.16b, v8.16b
  movi v6.16b, 0
  aesd v6.16b, v8.16b
  movi v7.16b, 0
  aesd v7.16b, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	155	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20111	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	0	20062	0	160000	100	20066	20066	20066	20066	20162
160204	20065	155	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	598	0	1	1	1	10119	0	16	0	20195	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	1	1	1	10119	0	16	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	29	25	80116	100	80123	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	641036	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	20281	0	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	34	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	20062	0	160000	100	20066	20066	20066	20066	20222
160204	20065	156	0	0	1	0	0	29	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	3	0	0	0	0	1	1	1	10119	0	16	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	124	25	80116	100	80016	100	80028	500	640196	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	20195	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	0	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20060	155	1	0	0	0	0	0	0	1	80	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	981	0	10041	6	4	2	1	31	26	3	2	2	26	26	20049	0	32	160000	10	20053	20054	20053	20053	20053
160024	20052	155	1	0	0	0	0	0	0	0	1815	25	80010	10	80000	10	80000	50	640000	0	1	20033	20053	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10049	6	4	2	1	28	26	3	2	2	29	29	20049	0	31	160000	10	20053	20053	20053	20053	20053
160024	20052	155	2	0	0	0	0	0	0	1	270	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10054	6	4	2	1	33	26	3	2	2	19	31	20049	0	31	160000	10	20053	20053	20053	20053	20053
160024	20052	155	2	0	0	0	0	0	0	0	80	25	80010	10	80000	10	80000	50	640000	0	1	20034	20053	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10057	6	4	2	1	29	26	3	2	2	20	31	20049	0	31	160000	10	20054	20053	20053	20053	20053
160024	20052	156	2	0	0	0	0	0	0	0	74	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10045	6	4	2	1	23	26	3	2	2	27	23	20049	0	31	160000	10	20053	20053	20053	20053	20053
160024	20052	155	1	0	0	0	0	0	0	0	57	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10057	6	4	2	1	31	26	3	2	2	29	16	20049	1	32	160000	10	20053	20053	20053	20053	20053
160024	20052	156	2	0	0	0	0	0	0	0	51	25	80010	10	80208	10	80000	50	640000	0	1	20033	20052	20212	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10055	6	4	2	1	30	26	3	2	2	20	31	20049	0	31	160000	10	20054	20053	20053	20053	20053
160024	20052	155	2	0	0	0	0	0	0	1	74	25	80010	10	80000	10	80000	50	640000	0	1	20034	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10053	6	4	2	1	23	26	3	2	2	32	19	20049	0	31	160000	10	20053	20053	20053	20053	20053
160024	20052	155	2	0	0	0	0	0	0	0	139	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	2	0	2	0	0	0	0	10057	6	4	2	1	32	26	3	2	2	29	30	20049	0	31	160000	10	20053	20053	20053	20053	20053
160024	20052	156	2	0	0	0	0	249	0	0	74	25	80010	10	80000	10	80000	50	640000	0	1	20033	20052	20052	3	22	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10058	6	4	2	1	31	26	3	2	2	30	31	20049	0	31	160000	10	20053	20053	20053	20053	20053

Test 5: throughput

Count: 16

Code:

  aesd v0.16b, v16.16b
  aesd v1.16b, v16.16b
  aesd v2.16b, v16.16b
  aesd v3.16b, v16.16b
  aesd v4.16b, v16.16b
  aesd v5.16b, v16.16b
  aesd v6.16b, v16.16b
  aesd v7.16b, v16.16b
  aesd v8.16b, v16.16b
  aesd v9.16b, v16.16b
  aesd v10.16b, v16.16b
  aesd v11.16b, v16.16b
  aesd v12.16b, v16.16b
  aesd v13.16b, v16.16b
  aesd v14.16b, v16.16b
  aesd v15.16b, v16.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	310	0	0	1	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	147	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40146	40040
160204	40039	311	1	0	1	0	0	0	9	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40090	40039	19977	6	20044	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	27	0	1	1	1	10118	3	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	0	1	0	0	0	0	0	204	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40154	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	30	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	0	1	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	7	0	9	0	1	1	1	10118	1	41	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	0	1	0	0	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	629	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	0	1	0	0	0	0	116	102	26	160116	100	160016	100	160435	500	1280196	0	40029	40049	40049	19976	9	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	7	0	12	0	2	2	2	10128	2	23	2	2	40046	160000	100	40049	40050	40050	40049	40049
160204	40048	311	0	0	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1284280	1	40029	40048	40049	19976	10	19986	160128	200	160038	200	320076	40048	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	34	0	0	0	2	2	2	10128	2	23	2	2	40045	160000	100	40049	40049	40050	40050	40050
160204	40049	310	0	0	0	0	0	0	0	0	454	26	160116	100	160016	100	160028	500	1280196	1	40029	40049	40048	19976	9	20014	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	10	0	9	2	2	2	2	10128	3	23	2	2	40046	160000	100	40049	40049	40049	40049	40049
160204	40048	311	0	0	0	0	2	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	0	40029	40048	40049	19976	9	19986	160128	200	160038	200	320076	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	6	0	9	0	2	2	2	10163	2	23	2	2	40045	160000	100	40049	40049	40049	40049	40050
160204	40048	310	0	0	0	0	0	0	0	0	64	26	160116	100	160016	100	160028	500	1280196	1	40029	40048	40049	19976	9	19986	160128	200	160038	200	320076	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	9	0	2	2	2	10128	2	23	2	2	40046	160000	100	40049	40049	40050	40049	40050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	310	0	0	1	0	0	0	0	0	270	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	0	16	20019	160010	20	160000	20	320000	40039	40140	1	1	160021	10	9	10	10	160000	10	0	2	0	0	0	0	0	0	0	10022	3	2	2	22	16	4	1	2	17	17	40036	30	10	160000	10	40040	40040	40088	40040	40040
160024	40039	311	0	0	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40108	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	2	10022	3	1	1	20	16	2	1	1	20	17	40036	15	5	160000	10	40040	40040	40068	40040	40040
160024	40039	310	0	0	0	0	2	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40175	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	3	1	1	20	16	2	1	1	19	21	40036	15	10	160000	10	40040	40040	40068	40040	40040
160024	40039	310	0	0	0	0	0	0	0	0	46	25	160010	10	160000	10	160106	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	2	0	525	0	0	10022	3	1	1	17	16	2	1	1	20	19	40036	15	5	160000	10	40040	40040	40066	40040	40040
160024	40039	311	0	0	0	0	0	0	0	116	46	25	160010	10	160000	10	160000	56	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	0	0	0	0	10022	3	1	1	17	16	2	1	1	20	20	40036	15	5	160000	10	40040	40040	40066	40040	40040
160024	40039	311	0	0	0	0	0	0	0	0	252	100	160010	10	160000	10	160000	50	1280836	0	1	40020	40144	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	2	0	0	0	0	0	0	0	0	10024	3	1	1	19	39	2	1	1	17	17	40036	15	5	160000	10	40040	40040	40068	40040	40040
160024	40039	311	0	0	0	1	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160211	20	320424	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	4	0	10022	3	1	1	18	16	2	1	1	14	16	40036	15	5	160000	10	40040	40040	40062	40040	40040
160024	40039	310	0	0	1	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	20024	0	3	20019	160010	20	160000	20	320000	40143	40039	1	1	160021	10	9	10	10	160000	10	2	0	0	0	3	0	0	0	0	10022	3	1	1	14	16	2	1	1	19	20	40036	15	5	160000	10	40040	40040	40065	40040	40040
160024	40039	310	0	0	0	0	0	0	0	0	331	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	0	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	1	0	0	0	0	10022	3	1	1	17	16	2	1	1	19	19	40036	17	5	160000	10	40040	40040	40064	40040	40040
160024	40039	311	0	0	0	0	0	0	0	0	46	25	160109	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	7	11	20099	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	5	4	0	0	0	10022	3	1	1	17	16	2	1	1	20	19	40036	15	5	160000	10	40040	40040	40071	40040	40040

AESD

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations