Firestorm: AESD + AESIMC measurements

Code:

  aesd v0.16b, v1.16b
  aesimc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
2004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	22	3	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  aesd v0.16b, v1.16b
  aesimc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	34433	241	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277300	1	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	2	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038
20204	30037	224	21	0	0	61	29548	25	10100	100	10000	100	10000	500	4277300	1	30018	30037	30037	27015	3	27495	10100	208	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	2	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	536	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	3	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	348	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	2	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	726	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	3	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	2	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	3	16	2	2	29931	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	1	63	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	2	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	2	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	1310	1	2	16	2	2	29885	0	20000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	33533	236	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	1	16	1	1	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	1	16	1	1	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	1	16	1	2	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	1	16	2	2	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	1	16	1	1	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	2	16	1	1	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	726	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	1	16	1	1	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	1	16	1	1	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	251	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1270	0	1	16	1	1	29884	0	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	232	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	1298	0	2	16	1	1	29884	0	20000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  aesd v0.16b, v0.16b
  aesimc v0.16b, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30037	225	0	0	0	0	0	0	0	536	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30084	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	0	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	2	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	61	29546	25	10100	102	10000	100	10000	500	4277147	0	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	64	29546	25	10100	100	10000	100	10000	500	4277147	0	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	0	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	536	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30126	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	0	0	726	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	1	1	1	1317	0	1	16	1	1	29888	0	20000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	a9	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30037	224	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27538	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30085	30038	30038
20024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	233	6	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	9	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	224	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	224	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	1	16	1	1	29883	20000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  aesd v0.16b, v8.16b
  aesimc v0.16b, v0.16b
  movi v1.16b, 0
  aesd v1.16b, v8.16b
  aesimc v1.16b, v1.16b
  movi v2.16b, 0
  aesd v2.16b, v8.16b
  aesimc v2.16b, v2.16b
  movi v3.16b, 0
  aesd v3.16b, v8.16b
  aesimc v3.16b, v3.16b
  movi v4.16b, 0
  aesd v4.16b, v8.16b
  aesimc v4.16b, v4.16b
  movi v5.16b, 0
  aesd v5.16b, v8.16b
  aesimc v5.16b, v5.16b
  movi v6.16b, 0
  aesd v6.16b, v8.16b
  aesimc v6.16b, v6.16b
  movi v7.16b, 0
  aesd v7.16b, v8.16b
  aesimc v7.16b, v7.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3758

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	30092	225	9	30	25	90112	100	90012	100	90021	500	750240	1	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	1	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	1	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	0	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	0	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	1	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	0	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	0	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	1	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	1	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	0	1	1	1	15119	16	30063	240000	100	30067	30067	30067	30067	30067

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3761

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	30228	226	0	0	0	0	0	0	6	339	25	90011	10	90000	10	90001	50	754878	5	1	5	30067	30089	30086	0	3	24	90010	20	160000	20	240000	30090	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	3	0	0	0	15114	140	22	13	25	58	12	12	7	6	15	30083	120	63	4	240000	10	30087	30087	30087	30087	30087
240024	30090	225	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	754878	5	1	5	30067	30086	30086	0	3	24	90010	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	60	0	0	0	15055	38	20	11	9	58	12	12	7	15	7	30083	120	63	4	240000	10	30087	30087	30087	30087	30087
240024	30086	225	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	754878	6	1	5	30067	30086	30086	0	3	24	90010	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	1	6	0	0	0	15048	38	20	11	7	58	12	12	7	5	14	30083	120	63	4	240000	10	30087	30087	30087	30087	30087
240024	30086	226	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	754878	5	1	5	30067	30086	30086	0	3	24	90010	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	6	0	0	0	15048	38	20	11	5	58	12	12	7	7	10	30083	120	63	4	240000	10	30109	30087	30109	30109	30087
240024	30086	225	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	754878	5	1	5	30089	30108	30108	0	3	24	90187	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	0	0	0	0	15046	38	20	11	8	58	12	12	7	14	6	30083	120	63	4	240000	10	30087	30087	30087	30087	30087
240024	30086	225	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	754878	5	1	5	30067	30086	30086	0	3	24	90010	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	3	0	1	0	15045	38	19	11	8	58	12	12	7	9	7	30083	120	63	4	240000	10	30087	30087	30087	30087	30087
240024	30086	225	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	754878	5	1	5	30067	30086	30086	0	3	24	90010	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	3	0	0	0	15044	38	22	11	12	81	12	12	7	9	9	30083	120	63	4	240000	10	30109	30109	30087	30087	30109
240024	30086	226	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	754878	6	1	5	30067	30086	30086	0	3	24	90010	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	9	0	0	0	15053	44	22	14	10	81	18	12	10	16	11	30104	176	63	4	240000	10	30087	30087	30087	30087	30087
240024	30086	226	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	754878	5	1	5	30067	30086	30090	0	3	24	90010	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	6	0	0	0	15047	38	19	11	7	58	12	12	7	7	15	30083	120	63	4	240000	10	30087	30087	30087	30087	30087
240024	30086	226	0	0	0	0	0	0	4	121	25	90010	10	90000	10	90000	50	753948	5	1	5	30067	30086	30086	0	3	24	90010	20	160000	20	240000	30086	30086	1	1	240021	10	9	10	10	240000	10	0	0	0	0	0	0	0	0	15053	38	19	11	8	58	12	12	7	12	7	30083	135	63	4	240000	10	30087	30090	30087	30087	30087

Test 5: throughput

Count: 16

Code:

  aesd v0.16b, v16.16b
  aesimc v0.16b, v0.16b
  aesd v1.16b, v16.16b
  aesimc v1.16b, v1.16b
  aesd v2.16b, v16.16b
  aesimc v2.16b, v2.16b
  aesd v3.16b, v16.16b
  aesimc v3.16b, v3.16b
  aesd v4.16b, v16.16b
  aesimc v4.16b, v4.16b
  aesd v5.16b, v16.16b
  aesimc v5.16b, v5.16b
  aesd v6.16b, v16.16b
  aesimc v6.16b, v6.16b
  aesd v7.16b, v16.16b
  aesimc v7.16b, v7.16b
  aesd v8.16b, v16.16b
  aesimc v8.16b, v8.16b
  aesd v9.16b, v16.16b
  aesimc v9.16b, v9.16b
  aesd v10.16b, v16.16b
  aesimc v10.16b, v10.16b
  aesd v11.16b, v16.16b
  aesimc v11.16b, v11.16b
  aesd v12.16b, v16.16b
  aesimc v12.16b, v12.16b
  aesd v13.16b, v16.16b
  aesimc v13.16b, v13.16b
  aesd v14.16b, v16.16b
  aesimc v14.16b, v14.16b
  aesd v15.16b, v16.16b
  aesimc v15.16b, v15.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2504

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320204	40091	300	0	740	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	978	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	163	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	140	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	142	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	636	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	73	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	161	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	140	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	779	25	160116	100	160016	100	160028	500	1280196	0	40045	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	1	1	20119	16	0	40064	320000	100	40068	40068	40068	40068	40068

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2550

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	41556	306	1	0	0	0	0	0	482	1647	230	160010	10	160000	10	160000	50	1280000	1	1	40776	40780	40787	3	22	160010	20	320000	20	480000	40796	40792	1	1	320021	10	9	10	10	320000	10	0	0	0	20357	340	202	116	34	771	137	141	54	24	21	40765	1334	253	339	320000	10	40786	40785	40800	41102	40781
320024	40765	306	0	0	0	0	0	0	404	1159	176	160010	10	160000	10	160000	50	1280000	1	1	40764	40780	40781	3	22	160010	20	320000	20	480000	40796	40780	1	1	320021	10	9	10	10	320000	10	0	0	0	20359	340	200	113	24	755	140	141	53	24	21	40748	1138	186	237	320000	10	40800	40782	40801	40784	40802
320024	40817	305	0	0	0	0	0	0	403	1643	177	160010	10	160000	10	160000	50	1280000	1	1	40761	40785	40799	3	22	160010	20	320000	20	480000	40818	40797	1	1	320021	10	9	10	10	320000	10	0	0	0	20357	336	200	116	19	738	134	141	53	20	20	40747	1187	210	246	320000	10	40781	40799	40782	40799	40783
320024	40786	305	0	0	0	0	9	0	406	1204	181	160010	10	160000	10	160000	50	1280000	0	1	40896	40779	40800	3	22	160010	20	320000	20	480000	40777	40770	1	1	320021	10	9	10	10	320000	10	0	3	0	20354	342	202	114	19	760	136	142	53	22	20	40748	1122	188	242	320000	10	40767	40785	40803	40790	40781
320024	40780	306	1	0	0	0	0	0	403	1224	183	160010	10	160000	10	160000	50	1280000	0	1	40766	40788	40786	3	22	160010	20	320000	20	480000	40780	40780	1	1	320021	10	9	10	10	320000	10	0	0	0	20364	345	202	116	21	769	159	158	58	22	23	40859	1303	253	252	320000	10	40786	40800	40781	40799	40801
320024	40782	305	0	0	0	0	0	0	401	975	176	160010	10	160000	10	160000	50	1280000	0	1	40762	40781	40783	3	22	160010	20	320000	20	480000	40818	40838	1	1	320021	10	9	10	10	320000	10	0	0	0	20365	343	202	113	21	757	137	138	54	24	20	40748	1123	189	229	320000	10	40796	40782	40799	40791	40781
320024	40782	306	0	0	0	0	0	0	392	1055	177	160010	10	160000	10	160000	50	1280000	0	1	40766	40780	40782	3	22	160010	20	320000	20	480000	40784	40783	1	1	320022	10	9	10	10	320000	10	0	0	0	20360	343	202	113	21	756	137	160	54	23	20	40765	1140	197	252	320000	10	40898	40800	40813	40800	40910
320024	40814	305	0	0	0	0	0	0	400	1101	182	160010	10	160000	10	160000	50	1280000	0	1	40765	40797	40816	3	22	160010	20	320000	20	480000	40795	40782	1	1	320021	10	9	10	10	320000	10	0	0	0	20353	343	202	113	23	773	135	142	54	20	20	40837	1173	204	260	320000	10	40782	40796	40780	40799	40783
320024	40782	305	0	0	0	0	0	0	398	1271	344	160010	10	160000	10	160000	50	1280000	0	1	40892	40800	40815	3	22	160010	20	320000	20	480000	40877	40811	1	1	320021	10	9	10	10	320000	10	0	0	0	20356	355	206	116	23	769	137	142	54	20	24	40761	1235	194	243	320000	10	40800	40800	40805	40783	40801
320024	40805	305	0	0	0	0	0	0	377	1089	180	160010	10	160000	10	160000	50	1280000	0	1	40781	40782	40780	3	22	160010	20	320000	20	480000	40800	40809	1	1	320021	10	9	10	10	320000	10	0	0	0	20360	337	202	117	21	773	139	142	55	23	16	40755	1144	188	254	320000	10	40783	40784	40807	40816	40832

AESD + AESIMC

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations