Firestorm: AESE + AESMC measurements

Code:

  aese v0.16b, v1.16b
  aesmc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
2004	3037	25	12	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	143	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	24	0	124	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	25	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	24	0	0	251	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	3	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	24	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3408	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	25	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	24	9	0	66	2548	25	1000	1170	1283	398313	0	3018	3037	3073	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	25	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038
2004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2290	3	2770	1000	2000	3000	3037	3037	1	1	2001	2000	0	0	0	0	136	16	2884	2000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  aese v0.16b, v1.16b
  aesmc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	34883	256	0	0	2	0	0	263	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1311	1	4	16	3	3	29885	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	1	64	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1311	1	3	16	3	3	29885	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	1	64	29548	25	10100	100	10000	100	10000	500	4277300	1	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1311	1	3	16	3	2	29885	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	1	87	29548	25	10100	100	10000	100	10000	500	4277300	1	30018	30037	30037	27015	3	27495	10100	200	20683	202	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1310	1	2	16	3	3	29885	20000	100	30038	30038	30038	30038	30038
20204	30037	224	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277300	1	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1311	1	3	16	3	3	29885	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	1	61	29548	25	10100	100	10000	100	10000	500	4277300	1	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1311	1	3	16	3	2	29885	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1310	1	2	16	3	3	29885	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	1	61	29548	25	10100	100	10000	100	10000	500	4277300	1	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1310	1	3	16	3	2	30094	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	1	64	29548	25	10100	100	10000	100	10000	500	4277300	1	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1310	1	2	16	3	3	29885	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	0	0	0	419	29548	25	10100	100	10000	100	10000	500	4277300	0	30018	30037	30037	27015	3	27495	10100	200	20000	200	30000	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	0	0	0	1310	1	3	16	3	2	29885	20000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	33535	236	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	2	16	1	3	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	1	16	1	2	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	1	16	2	3	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	1	16	3	4	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	1	16	1	3	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	2	16	1	3	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	1	16	1	3	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	1	16	1	1	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	1	16	1	1	29884	20000	10	30038	30038	30038	30038	30038
20024	30037	225	0	0	84	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	27037	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1270	0	1	16	1	3	29884	20000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  aese v0.16b, v0.16b
  aesmc v0.16b, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27022	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	61	29546	25	10100	100	10000	100	10000	500	4277147	1	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038
20204	30037	225	0	0	63	29546	25	10100	100	10000	100	10000	500	4277147	0	30018	30037	30037	27021	6	27491	10100	200	20008	200	30012	30037	30037	1	1	20201	100	99	100	100	20000	100	0	0	1	1	1	1317	0	1	16	1	1	29888	20000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
20024	30037	225	1	1	0	3	71	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	1276	22	16	12	15	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	1	1	0	3	71	29547	25	10010	10	10000	10	10000	50	4278511	0	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	1276	14	16	13	8	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	1	1	0	3	146	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	1276	13	16	11	13	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	1	1	0	3	71	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1	0	0	0	0	1276	13	16	10	14	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	1	1	0	3	71	29511	25	10010	10	10008	10	10000	50	4278511	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	8	0	0	0	0	1276	13	16	14	13	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	1	1	0	3	71	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	1276	14	16	12	12	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	1	1	0	3	71	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	2	1	0	0	0	0	1276	13	16	14	8	29883	20000	10	30134	30087	30038	30038	30038
20024	30037	226	1	1	1	3	113	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30037	1	1	20021	10	9	10	10	20000	10	0	0	0	0	0	0	1276	8	16	13	14	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	1	1	0	3	113	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	27036	3	27517	10010	20	20000	20	30267	30037	30037	1	1	20021	10	9	10	10	20000	10	0	1	0	3	0	0	1276	13	16	13	13	29883	20000	10	30038	30038	30038	30038	30038
20024	30037	225	1	1	0	3	71	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	27036	3	27517	10010	20	20000	20	30000	30037	30181	1	1	20021	10	9	10	10	20000	10	0	1	0	3	0	0	1276	14	16	12	13	29883	20000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  aese v0.16b, v8.16b
  aesmc v0.16b, v0.16b
  movi v1.16b, 0
  aese v1.16b, v8.16b
  aesmc v1.16b, v1.16b
  movi v2.16b, 0
  aese v2.16b, v8.16b
  aesmc v2.16b, v2.16b
  movi v3.16b, 0
  aese v3.16b, v8.16b
  aesmc v3.16b, v3.16b
  movi v4.16b, 0
  aese v4.16b, v8.16b
  aesmc v4.16b, v4.16b
  movi v5.16b, 0
  aese v5.16b, v8.16b
  aesmc v5.16b, v5.16b
  movi v6.16b, 0
  aese v6.16b, v8.16b
  aesmc v6.16b, v6.16b
  movi v7.16b, 0
  aese v7.16b, v8.16b
  aesmc v7.16b, v7.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3758

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240204	30091	225	96	30	25	90112	100	90012	100	90021	500	750240	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	1	1	1	15119	4	16	0	0	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	1	1	1	15119	0	16	0	0	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	24	30	25	90112	100	90012	100	90021	500	750240	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	1	1	1	15119	0	16	0	0	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	226	48	30	25	90112	100	90012	100	90021	500	750240	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	1	1	1	15119	0	16	0	0	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	0	30	25	90112	100	90012	100	90021	500	750240	30046	30066	30066	6	31	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	1	1	1	15119	0	16	0	0	30063	240000	100	30067	30067	30067	30067	30067
240204	30066	225	288	30	25	90112	100	90012	100	90021	500	750240	30046	30066	30066	6	13	90121	200	160037	200	240056	30066	30066	1	1	240201	100	99	100	100	240000	100	0	0	2	2	2	15131	1	23	1	1	30075	240000	100	30079	30079	30079	30079	30080
240204	30078	225	0	66	28	90114	100	90014	100	90023	500	750396	30057	30078	30078	9	13	90123	200	160041	200	240062	30078	30078	1	1	240201	100	99	100	100	240000	100	0	0	2	2	2	15131	1	23	1	1	30075	240000	100	30155	30079	30079	30080	30079
240204	30079	225	36	66	28	90114	100	90014	100	90023	500	750396	30057	30078	30079	9	13	90123	200	160041	200	240062	30078	30079	1	1	240201	100	99	100	100	240000	100	0	0	2	2	2	15131	1	23	1	1	30075	240000	100	30080	30079	30079	30079	30079
240204	30078	225	0	66	27	90114	100	90014	100	90023	500	750396	30057	30078	30078	10	13	90123	200	160041	200	240062	30079	30078	1	1	240201	100	99	100	100	240000	100	0	0	2	2	2	15131	1	23	1	1	30076	240000	100	30080	30079	30079	30079	30080
240204	30079	225	27	66	27	90114	100	90014	100	90023	500	750396	30057	30078	30078	9	13	90123	200	160041	200	240062	30078	30078	1	1	240201	100	99	100	100	240000	100	0	0	1	1	1	15121	2	24	2	2	30073	240000	100	30077	30077	30077	30077	30077

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3763

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240024	30191	225	0	0	0	0	3	33	0	3	94	38	90010	10	90001	10	90000	50	752833	2	1	5	31008	30109	30106	0	3	23	90010	20	160000	20	241137	30135	30084	1	1	240021	10	9	10	10	240000	10	0	0	0	15052	27	13	7	24	74	8	8	6	25	21	30093	117	57	17	240000	10	30103	30100	30103	30100	30100
240024	30102	226	0	0	0	0	0	6	0	3	94	38	90010	10	90000	10	90383	50	753093	3	1	5	30907	30099	30084	0	3	24	90010	20	160000	20	240000	30102	30181	1	1	240021	10	9	10	10	240000	10	21	0	0	15052	35	13	7	25	72	9	9	6	22	22	30095	101	57	17	240000	10	30103	30100	30103	30110	30103
240024	30084	225	0	0	0	0	0	39	0	2	88	38	90010	10	90000	10	90000	50	756627	5	1	10	30897	30099	30084	0	3	24	90010	20	160000	20	240000	30102	30102	1	1	240021	10	9	10	10	240000	10	0	0	0	15052	49	13	7	18	72	8	8	6	9	21	30093	117	54	17	240000	10	30103	30308	30100	30100	30103
240024	30084	226	0	0	0	0	0	36	0	3	88	38	90010	10	90000	10	90000	50	753093	3	1	10	30903	30099	30084	0	3	133	90010	20	160000	20	240000	30102	30099	1	1	240021	10	9	10	10	240000	10	0	0	0	15042	32	15	7	23	74	8	8	6	12	22	30095	117	54	17	240000	10	30103	30100	30100	30103	30103
240024	30084	225	0	0	0	0	0	27	0	3	98	38	90010	10	90000	10	90000	50	748382	4	1	10	30933	30102	30099	0	3	24	90010	20	160000	20	240000	30102	30102	1	1	240021	10	9	10	10	240000	10	0	0	0	15053	45	15	7	19	72	8	8	6	19	23	30093	117	54	17	240000	10	30103	30100	30100	30100	30103
240024	30084	225	0	0	0	0	0	27	0	3	94	38	90010	10	90160	10	90000	50	753093	3	1	10	30908	30099	30102	0	3	24	90010	20	160181	20	240000	30134	30102	1	1	240021	10	9	10	10	240000	10	0	0	0	15051	32	13	7	19	72	8	8	6	19	11	30093	117	57	19	240000	10	30103	30100	30100	30100	30103
240024	30102	225	0	0	0	0	0	27	0	5	114	38	90010	10	90000	10	90000	50	753093	3	1	10	30911	30102	30099	0	3	23	90010	20	160000	20	240000	30102	30102	1	1	240021	10	9	10	10	240000	10	0	3	0	15062	57	27	15	28	118	16	16	11	28	14	30139	197	81	10	240000	10	30100	30100	30085	30100	30100
240024	30084	226	0	0	0	0	0	0	0	3	88	38	90010	10	90000	10	90000	50	753093	3	1	10	30951	30102	30099	0	3	24	90010	20	160000	20	240000	30084	30102	1	1	240021	10	9	10	10	240000	10	0	0	0	15049	32	13	7	19	72	8	8	6	10	23	30093	117	54	17	240000	10	30103	30100	30100	30100	30103
240024	30102	225	0	0	0	0	0	33	0	3	88	38	90010	10	90000	10	90000	50	753093	3	1	10	30890	30154	30151	0	3	24	90010	20	160000	20	240000	30148	30134	1	1	240021	10	9	10	10	240000	10	0	0	0	15039	32	13	7	18	72	8	8	6	19	19	30093	117	54	17	240000	10	30103	30109	30100	30100	30103
240024	30102	226	0	0	0	0	0	24	0	4	94	38	90010	10	90000	10	90000	50	753093	3	1	10	30942	30131	30084	0	3	23	90010	20	160000	20	240000	30102	30109	1	1	240021	10	9	10	10	240000	10	0	0	0	15056	35	13	8	19	72	10	8	7	22	9	30093	117	54	17	240000	10	30103	30100	30100	30100	30100

Test 5: throughput

Count: 16

Code:

  aese v0.16b, v16.16b
  aesmc v0.16b, v0.16b
  aese v1.16b, v16.16b
  aesmc v1.16b, v1.16b
  aese v2.16b, v16.16b
  aesmc v2.16b, v2.16b
  aese v3.16b, v16.16b
  aesmc v3.16b, v3.16b
  aese v4.16b, v16.16b
  aesmc v4.16b, v4.16b
  aese v5.16b, v16.16b
  aesmc v5.16b, v5.16b
  aese v6.16b, v16.16b
  aesmc v6.16b, v6.16b
  aese v7.16b, v16.16b
  aesmc v7.16b, v7.16b
  aese v8.16b, v16.16b
  aesmc v8.16b, v8.16b
  aese v9.16b, v16.16b
  aesmc v9.16b, v9.16b
  aese v10.16b, v16.16b
  aesmc v10.16b, v10.16b
  aese v11.16b, v16.16b
  aesmc v11.16b, v11.16b
  aese v12.16b, v16.16b
  aesmc v12.16b, v12.16b
  aese v13.16b, v16.16b
  aesmc v13.16b, v13.16b
  aese v14.16b, v16.16b
  aesmc v14.16b, v14.16b
  aese v15.16b, v16.16b
  aesmc v15.16b, v15.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2504

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320204	40092	300	0	0	31	25	160116	100	160016	100	160028	500	1280196	1	0	40051	0	40067	40067	0	6	14	160128	200	320056	202	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	1	0	3	0	1	1	1	20126	0	0	2	16	3	3	40064	0	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	0	31	25	160116	100	160016	100	160028	500	1280196	1	0	40045	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	0	0	728	0	1	1	1	20122	0	0	3	16	5	5	40271	0	320000	100	40068	40068	40310	40068	40068
320204	40067	300	30	0	31	25	160116	100	160016	100	160028	500	1280196	0	5	40045	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	0	0	0	0	1	1	1	20122	5	3	3	16	4	3	40064	0	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	0	31	25	160116	100	160016	100	160028	500	1280196	1	0	40045	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	2	0	0	0	0	0	1	1	1	20121	5	4	3	16	2	4	40163	0	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	0	31	25	160116	100	160016	100	160028	500	1280196	1	5	40045	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	0	0	0	0	1	1	1	20124	5	4	3	16	3	2	40064	0	320000	100	40068	40068	40068	40068	40068
320204	40067	300	0	0	31	25	160116	100	160016	100	160028	500	1280196	1	5	40045	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	0	0	0	0	1	1	1	20122	5	4	3	16	3	6	40064	0	320000	100	40068	40068	40068	40068	40068
320204	40067	300	24	0	31	25	160116	100	160016	100	160028	500	1280196	1	5	40045	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	0	0	0	0	1	1	1	20120	5	4	3	16	5	3	40064	0	320000	100	40068	40068	40068	40068	40068
320204	40067	300	36	0	31	25	160116	100	160016	100	160028	500	1280196	1	5	40045	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	0	0	0	0	1	1	1	20123	5	4	3	16	4	5	40064	0	320000	100	40068	40068	40068	40068	40068
320204	40067	300	9	88	31	25	160116	100	160016	100	160028	500	1280196	1	5	40052	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	0	0	0	0	1	1	1	20124	5	4	4	16	1	3	40064	0	320000	100	40068	40068	40068	40068	40068
320204	40067	300	6	0	696	25	160116	100	160016	100	160028	500	1280196	1	5	40045	0	40067	40067	0	6	14	160128	200	320056	200	480084	40067	40067	1	1	320201	100	99	100	100	320000	100	0	0	0	0	0	0	1	1	1	20122	5	4	3	16	4	4	40064	0	320000	100	40068	40068	40068	40068	40068

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2560

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320024	41230	308	6	3	0	0	0	0	88	1019	295	160010	10	160000	10	160000	50	1280000	3	1	5	43108	0	40976	40954	0	3	22	160010	20	320000	20	480000	40931	40952	1	1	320021	10	9	10	10	320000	10	48	0	0	20365	371	186	121	2	36	943	147	140	68	26	12	40844	1302	281	330	320000	10	40983	41021	41029	40969	40906
320024	40944	307	5	3	0	0	0	0	71	946	326	160010	10	160000	10	160000	50	1280000	7	1	5	42949	0	40963	40944	0	3	22	160010	20	320000	20	480000	40942	40942	1	1	320021	10	9	10	10	320000	10	0	93	0	20405	380	194	124	2	24	1017	159	163	74	28	13	40860	1318	295	333	320000	10	41027	41027	41025	41027	40961
320024	40918	306	4	4	0	0	0	0	76	972	297	160010	10	160000	10	160000	50	1280000	4	1	5	42863	3	40964	40927	0	3	22	160010	20	320000	20	480000	40959	40918	1	1	320021	10	9	10	10	320000	10	0	0	0	20391	349	191	117	2	24	892	156	139	70	24	9	40819	1310	283	335	320000	10	40907	40943	40907	40907	40949
320024	40906	306	3	2	0	0	0	0	80	949	295	160010	10	160000	10	160000	50	1280000	4	1	5	42699	0	41087	41016	0	3	22	160010	20	320000	20	480000	40958	40958	1	1	320021	10	9	10	10	320000	10	0	0	0	20386	379	191	116	2	11	1045	180	163	75	24	11	40947	1320	290	335	320000	10	40959	41046	40933	40961	41059
320024	41012	306	3	4	0	0	9	0	89	974	294	160010	10	160000	10	160000	50	1280000	8	1	5	42932	0	40982	41125	0	3	22	160010	20	320000	20	480000	40958	40958	1	1	320021	10	9	10	10	320000	10	0	0	0	20399	359	199	117	2	11	904	155	142	70	25	12	40872	1318	282	333	320000	10	40959	40931	40959	40959	40937
320025	40952	307	3	2	0	0	0	0	82	1000	288	160010	10	160000	10	160000	50	1280000	0	1	5	42733	0	41065	41116	0	3	22	160010	20	320000	20	480000	40930	40930	1	1	320021	10	9	10	10	320000	10	0	0	0	20386	371	199	117	2	25	882	149	147	72	26	11	40844	1318	300	333	320000	10	40933	40931	40932	40932	40959
320024	40958	306	3	2	0	0	0	0	82	954	289	160010	10	160000	10	160000	50	1280000	0	1	5	42809	0	41105	41069	0	3	22	160010	20	320000	20	480000	40930	40930	1	1	320021	10	9	10	10	320000	10	0	0	0	20371	359	203	123	2	12	932	151	147	71	26	11	40844	1462	356	405	320000	10	41059	41059	41060	41032	41059
320024	41058	308	3	4	0	0	0	0	88	1031	294	160010	10	160000	10	160000	50	1280000	0	1	5	42922	0	41018	41108	0	3	22	160010	20	320000	20	480000	40958	40958	1	1	320021	10	9	10	10	320000	10	0	0	0	20375	347	315	126	2	26	974	175	158	72	27	11	40872	1305	300	333	320000	10	40931	40959	40931	40931	41032
320024	41083	308	4	3	0	0	0	0	88	1060	295	160010	10	160000	10	160000	50	1280000	4	1	5	42904	0	41032	41088	0	3	22	160010	20	320000	20	480000	41058	41059	1	1	320021	10	9	10	10	320000	10	0	3	0	20385	371	190	121	1	28	934	155	148	70	14	22	40852	1462	356	414	320000	10	40941	40928	40987	40950	40959
320024	40958	306	3	3	0	0	0	0	80	949	294	160010	10	160000	10	160000	50	1280000	4	1	5	42778	0	41070	40925	0	3	22	160010	20	320000	20	480000	41040	41007	1	1	320021	10	9	10	10	320000	10	0	0	0	20384	358	202	121	1	27	981	171	160	74	22	11	40941	1399	345	387	320000	10	40931	40931	40941	40943	40943

AESE + AESMC

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations