Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

AESIMC

Test 1: uops

Code:

  aesimc v0.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371566116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371536116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316221786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038

Test 2: Latency 1->2

Code:

  aesimc v0.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)181e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037155000000014519686251010010010000100100005002847521200180200372008418421318745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038
102042003715500000006119686251010010010000100100005002847521200180200372003718421318745101002001000020010000200372003721102011009910010010000100000000071021622197910100001002003820038200382003820038
102042003715500000006119686251013510010000100100005002847521200180200372003718421718745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038
102042003715600000006119686251010010010000100100005002847521200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820085200382003820038
1020420037155000000061196862510100100100001001000050028475212001802003720037184213187451010020010000200100002003720037111020110099100100100001000004603071021622197910100001002008620038200382003820038
102042003715500000006119686251010010010000121100005002847521200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622198600100001002003820038200382003820038
102042003715500000006119686251010010010000100100005002847521200180200372003718421318745101002001000020010000200372003711102011009910010010000100020000071021622197910100001002003820038200382003820038
102042003715600000006119686251010010010000100100005002847521200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622198620100001002003820038201332008520038
102042003715500000006119686251010010010000100100005002847521200180200372003718421318745101002001000020010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038
10204200371550000000113119686451010010010024117100005002847521200180200372003718421318745101002001033120010000200372003711102011009910010010000100000000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371560000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102013320038200382003820038
10024200371550000000061196862510010101000010100005028475210200182003720037184438187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371550000000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371560000000161196862510010101000010100005028500490200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
1002420037155000010320061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000001006402162219786010000102003820038200382003820038
10024200371550000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371550000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001002000006402162219786010000102003820038200382003820038
10024200371550000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371550010000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000000006402162219786010000102003820038200382003820038
10024200371560000000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001020200611506402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  aesimc v0.16b, v8.16b
  aesimc v1.16b, v8.16b
  aesimc v2.16b, v8.16b
  aesimc v3.16b, v8.16b
  aesimc v4.16b, v8.16b
  aesimc v5.16b, v8.16b
  aesimc v6.16b, v8.16b
  aesimc v7.16b, v8.16b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059155010100436258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000111511801600200350800001002003920039200392003920039
802042003815600000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000111511801600200350800001002003920039200392003920039
8020420038155000000138258010810080008100800205006401321200192003820094997769989801202008003220080135200382003811802011009910010080000100000000111511801600200350800001002003920039200392003920039
80204200381550020007392580108100800081008002050064013212001920038200381000469989801202008003220080032200382003811802011009910010080000100000004111513701600200350800001002003920039200392003920039
802042003815600000052258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000111511801600200350800001002003920039200392003920039
802042003815500000132151258010810080008100800205006401320200192003820038997769989801202008003220080032200382003811802011009910010080000100000004111511801600200350800001002003920039200392003920039
8020420038155000000136258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000000111511801600200350800001002003920039200392003920039
8020420038155000000136258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100001000111511823000200350800001002003920039200392003920039
8020420038156000000918258010810080008100800205006401321200192003820138997769989801202008003220080032200382003811802011009910010080000100000000111511801600200350800001002003920039200392003920039
802042010815600000092258010810080008100800205006401321200192003820087998569989801202008003220080032200382003811802011009910010080000100000000111511801600200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115600000000872580102108009310800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000005020216552003580000102003920039201072003920039
800242003815600000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200382180021109101080000100000005020416342003580000102003920039200392003920039
800242003815600000000398280010108018710800005064000012007620038200889996310018800102080097208009820038200381180021109101080000100000005020316332003580000102003920039200392003920112
8002420038155001001328802922580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000005020416452003580000102003920039200392003920039
8002420038155001200001232580010108000010800005064000002001920038200389996310071800102080000208000020038200381180021109101080000100000005020716342003580000102003920089200392003920039
800242003815500000000392580010108000010800005064000002001920038200909996310018801072080000208000020038200381180021109101080000100000005020216552003580000102003920039200392003920039
800242003815500000000392580198108000010800975064000002001920038200389996310018800102080000208000020038200381180021109101080000100000005020416442003580000102003920088200392003920039
800242003815600000000606080010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000005020440342003580000102003920039200392003920039
800242003815500000000832580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100202005020316552003580000102003920039200392003920039
8002420038155000000007292580010108000010800005064000002001920038200389996310018800102080000208000020109200381180021109101080000100000005020316442003580000102003920039200392003920039