Firestorm: AESMC measurements

Code:

  aesmc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	54	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	69	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	81	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	9	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	9	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->2

Code:

  aesmc v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	155	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19824	0	10000	100	20038	20137	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	83	19686	25	10100	100	10000	100	10000	500	2847521	20054	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	2127	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	3	18745	10100	204	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	904	19686	25	10100	100	10012	100	10150	500	2847521	20018	20037	20037	18421	3	18745	10422	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	12	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20132	20038	20038
10204	20037	156	0	0	0	0	9	0	0	353	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	3	18745	10100	200	10000	204	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19826	0	10000	100	20038	20038	20038	20038	20085
10204	20037	155	0	0	0	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	0	0	0	0	0	0	172	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	0	105	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18421	3	18780	10100	200	10000	212	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	156	0	0	0	0	0	0	0	105	19686	25	10100	100	10000	100	10000	500	2850049	20018	20037	20037	18421	3	18745	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	6	3	0	0	710	2	16	2	3	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	84	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10304	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	5	2	19822	0	10000	10	20038	20038	20038	20038	20038
10024	20084	155	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10170	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	84	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	105	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19822	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10152	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10163	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	156	0	0	0	0	0	0	0	0	1084	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	0	0	149	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20084	20038
10024	20037	155	0	0	1	0	0	0	0	0	105	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10316	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	0	10000	10	20038	20085	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  aesmc v0.16b, v8.16b
  aesmc v1.16b, v8.16b
  aesmc v2.16b, v8.16b
  aesmc v3.16b, v8.16b
  aesmc v4.16b, v8.16b
  aesmc v5.16b, v8.16b
  aesmc v6.16b, v8.16b
  aesmc v7.16b, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20058	155	0	0	0	0	0	0	0	0	0	50	25	80108	100	80008	100	80020	500	641708	1	20028	20048	20048	9976	10	9986	80128	200	80038	200	80038	20049	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	11	2	2	2	5128	2	23	1	2	20045	0	80000	100	20049	20049	20049	20050	20050
80204	20049	156	0	0	0	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	1	20028	20049	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	2	44	3	2	20045	0	80000	100	20049	20049	20049	20097	20049
80204	20048	155	0	0	0	0	0	0	0	0	0	64	27	80116	100	80016	100	80124	500	640196	1	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	515	0	2	2	2	5129	2	23	3	2	20045	0	80000	100	20049	20049	20049	20050	20049
80204	20048	155	0	0	0	0	0	0	0	0	0	120	27	80116	100	80016	100	80028	500	640196	1	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20049	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	3	23	1	3	20045	0	80000	100	20154	20050	20050	20049	20049
80204	20049	155	0	0	0	0	0	0	0	0	0	64	27	80116	100	80111	100	80127	500	640196	0	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20049	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5129	3	23	1	3	20046	0	80000	100	20049	20049	20049	20049	20049
80204	20048	156	0	0	0	0	0	0	0	0	0	64	27	80116	100	80016	100	80028	500	640196	1	20028	20049	20048	9976	10	9986	80128	200	80038	200	80038	20049	20049	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	3	23	1	2	20045	0	80000	100	20050	20049	20049	20049	20050
80204	20048	155	0	0	0	0	0	0	0	0	0	64	27	80116	100	80016	100	80028	500	640196	0	20028	20048	20048	9976	9	9986	80128	200	80038	200	80038	20048	20049	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	3	23	1	2	20045	0	80000	100	20150	20050	20050	20050	20049
80204	20049	155	0	0	0	0	0	0	0	0	0	64	27	80116	100	80016	100	80028	500	640196	1	20028	20049	20048	9976	9	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	3	23	2	3	20046	0	80000	100	20050	20049	20049	20049	20049
80204	20048	155	0	0	0	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	1	20028	20048	20048	9976	10	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	0	0	0	2	2	2	5128	3	23	1	2	20045	0	80000	100	20104	20049	20049	20050	20049
80204	20048	156	1	0	0	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20028	20048	20049	9976	10	9986	80128	200	80038	200	80038	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	1	0	465	0	2	2	2	5128	2	23	1	3	20045	0	80000	100	20049	20113	20113	20049	20050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20050	155	0	0	0	0	0	165	88	0	62	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9996	3	10018	80106	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	465	7	5020	12	16	2	7	5	20035	80000	10	20039	20039	20039	20099	20039
80024	20038	155	0	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20100	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	2	0	0	0	0	0	5020	5	16	2	7	5	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20237	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	4	16	0	6	4	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	0	0	3	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	4	0	0	0	0	0	0	5020	4	16	0	6	6	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	0	0	0	0	81	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	3	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	5	16	0	6	6	20035	80000	10	20087	20039	20039	20039	20039
80024	20038	155	0	0	0	0	0	0	0	0	373	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	10012	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	7	16	0	6	7	20035	80000	10	20039	20039	20244	20039	20039
80024	20038	156	0	0	0	0	0	12	0	0	39	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	468	0	5020	5	16	0	5	7	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	155	0	0	0	0	0	0	0	0	39	25	80010	10	80094	10	80000	50	640760	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	2	3	0	5020	6	16	2	7	7	20035	80000	10	20039	20039	20039	20039	20039
80024	20186	155	0	0	0	0	0	0	0	0	39	25	80010	10	80000	10	80000	50	640000	0	1	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	0	0	5020	4	16	0	5	6	20035	80000	10	20039	20039	20039	20039	20039
80024	20038	156	0	0	0	0	0	12	132	0	62	25	80010	10	80000	10	80000	50	640000	0	0	20019	20038	20038	9996	3	10018	80010	20	80000	20	80000	20038	20038	4	1	80021	10	9	10	10	80000	10	0	0	2	0	1	0	0	0	5020	7	16	0	7	8	20035	80000	10	20039	20101	20039	20039	20039

AESMC

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations