Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

AND (vector, 16B)

Test 1: uops

Code:

  and v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500113168725100010001000264680020182037203715723189510001000200020372037111001100000373216211787100020382038203820382038
10042037160085168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
1004203716019861168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037150084168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037150073168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000150073116111787100020382038203820382038
10042037160082168725100010001000264680020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
10042037160082168725100010001000264680120182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371501561168725100010001000264680120182037203715723189510001000200020372037111001100001073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  and v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150287611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042008415000611968725101001001000010010000500284807012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715500611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
1020420037150002321968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000100640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
1002420037150000156196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  and v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197919100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510257200100002002000020037200371110201100991001001000010000071021622197910100001002008420038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100093071021622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100051071031622197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371490007261968725100101010000101000050284768020018200372003718444318767100102010000202000020084200371110021109101010000100006405165519785010000102003820038200382003820038
10024200371500006311968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100036406165619785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100106406165619785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768020018200372003718444318767100102010000202000020085200371110021109101010000103306406164619785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006404165519785010000102003820038200382003820038
1002420037150000841968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006406164619785010000102003820038200382003820038
1002420037149000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006406165619785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006406166519785010000102003820038200382003820038
1002420037149000611968725100101010000101030450284768020018200372003718444318767100102010000202000020037200371110021109101010000100066406165419785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100006405165519785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  and v0.16b, v8.16b, v9.16b
  and v1.16b, v8.16b, v9.16b
  and v2.16b, v8.16b, v9.16b
  and v3.16b, v8.16b, v9.16b
  and v4.16b, v8.16b, v9.16b
  and v5.16b, v8.16b, v9.16b
  and v6.16b, v8.16b, v9.16b
  and v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060151040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051102161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000951101161120035800001002003920039200392003920039
80204200381509922258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150940258010010080000100800005006400000200192008820038997303999680100200800002001600002003820038118020110099100100800001000351101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)d9daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500003925800101380000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010100502061600562003580000102003920039200392003920039
800242003815009041925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000502031600532003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000502051600542003580000102003920039200392003920039
80024200381490003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010200502051600532003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000502031600352003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000502031600352003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000502031600352003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010160502051600352003580000102003920039200392003920039
800242003815000039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100960502031600532003580000102003920039200392003920039
80024200381500003925800101080000108000050640000120019020038200389996310018800102080000201600002003820038118002110910108000010000502031600352003580000102003920039200392003920039