Firestorm: BIC (vector, immediate, 2S) measurements

Code:

  bic v0.2s, #1

Initialization

  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	3	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	17	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	3	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	103	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	21	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1686	25	1000	1000	1000	264521	0	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	0	0	1	16	1	1	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bic v0.2s, #1

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	718	0	16	0	0	19801	10000	100	20182	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	5	0	0	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	42	0	168	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	50	0	3	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	33	1	1	1	718	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	81	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	0	483	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	3	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	82	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	4	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	18	0	72	0	640	3	16	3	4	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	641	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	4	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	3	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	3	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	66	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	187	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	4	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	235	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	4	5	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	4	19786	0	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  bic v0.2s, #1
  movi v1.16b, 0
  bic v1.2s, #1
  movi v2.16b, 0
  bic v2.2s, #1
  movi v3.16b, 0
  bic v3.2s, #1
  movi v4.16b, 0
  bic v4.2s, #1
  movi v5.16b, 0
  bic v5.2s, #1
  movi v6.16b, 0
  bic v6.2s, #1
  movi v7.16b, 0
  bic v7.2s, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	9	623	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	152	0	0	323	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	204	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	1	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	40	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	1	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	1	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	432	1075	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20162	150	1	0	104	44	27	80012	12	80000	12	80000	62	640000	1	1	0	20031	20050	20050	3	21	80012	20	80000	20	80000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	8	1	1	8	25	2	1	1	9	10	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	172	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	80000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10035	11	1	2	9	25	4	1	2	12	11	20047	2	41	0	1	160000	10	20062	20062	20060	20060	20060
160024	20061	150	0	12	0	118	27	80012	12	80000	12	80000	62	640000	0	1	5	20031	20050	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10035	11	1	2	11	34	4	1	2	10	10	20047	2	20	0	2	160000	10	20062	20060	20060	20051	20060
160024	20059	150	0	273	0	50	113	80012	12	80000	12	80000	62	640000	0	1	5	20040	20138	20059	9	60	80012	20	80194	20	80100	20129	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10032	11	2	1	9	34	2	2	2	10	12	20056	2	40	0	2	160000	10	20062	20051	20060	20060	20062
160024	20061	150	0	0	0	44	29	80012	12	80000	12	80125	62	640000	0	1	5	20031	20050	20059	3	21	80012	20	80000	20	80000	20050	20061	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	11	2	2	11	25	2	2	2	9	8	20056	2	20	0	2	160000	10	20060	20060	20051	20060	20060
160024	20061	150	0	12	0	44	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	20059	20059	3	21	80012	20	80000	20	80000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10035	11	2	2	12	34	2	2	2	9	9	20056	2	20	0	1	160000	10	20060	20051	20051	20060	20060
160024	20059	150	0	0	0	50	29	80012	12	80000	12	80000	62	640000	1	1	5	20040	20050	20061	3	21	80012	20	80000	20	80000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10035	11	1	2	10	34	4	2	2	10	11	20047	2	40	0	1	160000	10	20062	20051	20062	20060	20062
160024	20059	150	0	0	0	336	27	80012	12	80000	12	80000	62	640000	0	1	5	20040	20059	20059	3	21	80012	20	80000	20	80000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10037	11	1	2	11	25	2	2	2	9	9	20047	2	40	0	2	160000	10	20060	20060	20051	20060	20060
160024	20050	151	0	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	20061	20050	3	21	80012	20	80000	20	80000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10037	8	2	2	12	25	2	2	1	12	11	20056	2	40	0	2	160000	10	20062	20062	20060	20060	20051
160024	20050	150	0	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20031	20059	20050	3	21	80012	20	80000	20	80000	20059	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	8	1	2	9	34	3	2	2	10	10	20056	2	41	0	2	160000	10	20062	20060	20060	20051	20060

Test 4: throughput

Count: 16

Code:

  bic v0.2s, #1
  bic v1.2s, #1
  bic v2.2s, #1
  bic v3.2s, #1
  bic v4.2s, #1
  bic v5.2s, #1
  bic v6.2s, #1
  bic v7.2s, #1
  bic v8.2s, #1
  bic v9.2s, #1
  bic v10.2s, #1
  bic v11.2s, #1
  bic v12.2s, #1
  bic v13.2s, #1
  bic v14.2s, #1
  bic v15.2s, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40038	300	0	0	0	0	0	210	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	256	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	214	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	308	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	669	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	12	0	0	493	25	160100	100	160000	100	160000	500	1120016	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	439	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	229	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	544	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	0	0	0	0	0	0	1	927	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10076	8	3	1	12	16	2	1	1	12	15	40035	20	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1120016	0	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10075	8	3	1	12	16	2	1	1	9	13	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	1	0	0	0	0	0	0	55	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	3	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10080	11	3	2	17	16	4	1	1	9	15	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10090	8	2	1	15	16	2	1	1	14	14	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10073	11	2	1	14	16	2	1	1	14	16	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10075	8	2	2	8	16	2	1	1	16	13	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40088	300	0	0	0	0	0	0	0	0	710	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10075	8	3	2	15	16	2	1	1	13	15	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10075	11	2	1	14	16	2	1	1	11	14	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10077	11	3	1	10	16	2	1	1	14	13	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	0	40038	40038	19996	0	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	1	10074	8	2	1	15	16	2	1	1	15	13	40035	20	8	160000	10	40039	40039	40039	40039	40039

BIC (vector, immediate, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations