Firestorm: BIC (vector, immediate, 4H) measurements

Code:

  bic v0.4h, #1

Initialization

  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2084	15	1	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	84	1686	25	1000	1000	1000	264521	1	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	0	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	73	2	16	2	2	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bic v0.4h, #1

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	9	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	3	1	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	1	1	1	722	2	24	3	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	18	1	762	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	21	1	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	12	1	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	12	1	97	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18409	6	18733	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	149	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	36	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	7	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20084	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  bic v0.4h, #1
  movi v1.16b, 0
  bic v1.4h, #1
  movi v2.16b, 0
  bic v2.4h, #1
  movi v3.16b, 0
  bic v3.4h, #1
  movi v4.16b, 0
  bic v4.4h, #1
  movi v5.16b, 0
  bic v5.4h, #1
  movi v6.16b, 0
  bic v6.4h, #1
  movi v7.16b, 0
  bic v7.4h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	151	0	0	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10113	3	16	4	4	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	0	0	1	800	293	80614	117	80596	119	80596	638	644752	20429	20610	20222	29	103	80519	202	80401	200	80490	20534	20611	7	1	160201	100	99	100	100	160000	100	0	2	2	0	1	0	2888	0	10230	3	244	3	3	20384	21	160000	100	20613	20582	20597	20494	20537
160204	20570	153	1	1	0	6	7	675	440	0	1251	257	80812	123	80596	121	80498	614	643992	20470	20506	20457	50	142	80714	202	80400	200	80498	20612	20531	7	1	160201	100	99	100	100	160000	100	2	2	0	0	1	0	2153	0	10231	4	178	3	6	20383	22	160000	100	20405	20455	20399	20537	20513
160204	20454	153	1	0	1	0	0	276	264	0	549	218	80621	122	80502	119	80503	625	644016	20403	20534	20404	3	63	80420	202	80300	202	80297	20297	20298	5	1	160201	100	99	100	100	160000	100	0	2	2	0	1	0	2508	4	10231	3	173	4	2	20422	21	160000	100	20456	20459	20407	20454	20455
160204	20454	152	1	0	0	5	5	663	440	0	1034	220	80722	118	80497	121	80499	626	644736	20362	20455	20508	34	122	80721	200	80399	200	80495	20461	20455	6	1	160201	100	99	100	100	160000	100	4	0	2	0	0	0	2413	4	10255	4	214	4	3	20384	19	160000	100	20495	20457	20449	20480	20373
160204	20457	153	1	0	0	5	6	675	440	0	982	224	80725	118	80601	126	80498	654	643152	20363	20458	20453	34	140	80719	202	80503	202	80490	20455	20444	7	1	160201	100	99	100	100	160000	100	0	0	0	0	1	2	2508	0	10255	3	243	3	5	20450	20	160000	100	20561	20533	20532	20533	20563
160204	20531	154	1	0	1	7	7	804	528	0	1159	254	80725	123	80700	123	80689	632	644792	20428	20539	20534	34	21	80411	204	80498	202	80501	20404	20459	6	1	160201	100	99	100	100	160000	100	0	4	2	0	0	2	2398	2	10210	3	179	3	3	20320	18	160000	100	20378	20376	20453	20376	20531
160204	20449	151	0	0	1	5	6	807	616	0	791	202	80516	119	80498	122	80499	631	643952	20323	20377	20374	27	100	80618	202	80402	200	80390	20373	20404	6	1	160201	100	99	100	100	160000	100	4	0	2	1	0	0	2415	0	10113	3	16	3	3	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	6	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10113	4	16	3	3	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	24	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10113	3	16	3	3	20060	0	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	150	0	0	0	0	0	113	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	12	10025	8	3	1	9	20	2	1	1	2	4	20042	2	15	0	160000	10	20046	20046	20050	20050	20046
160024	20045	150	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	78	10027	8	3	1	2	20	2	1	1	4	2	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	3	10025	8	3	1	6	24	4	2	1	6	3	20042	2	15	0	160000	10	20046	20050	20046	20046	20046
160024	20045	150	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	8	3	1	4	20	2	1	1	4	2	20042	2	30	0	160000	10	20050	20046	20046	20046	20046
160024	20045	151	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10025	8	3	1	4	20	2	1	1	4	2	20042	1	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20049	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	8	3	1	2	20	2	1	1	2	4	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	1	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	90	10027	8	2	1	4	20	2	1	1	4	2	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	99	10027	8	3	1	4	20	2	1	1	2	4	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	24	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20028	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	10027	8	3	1	4	20	2	1	1	2	4	20042	2	47	30	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	5	20026	20045	20045	3	21	80012	20	80000	20	80000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	75	10026	8	3	1	4	24	2	1	1	4	2	20042	2	15	0	160000	10	20046	20046	20046	20046	20046

Test 4: throughput

Count: 16

Code:

  bic v0.4h, #1
  bic v1.4h, #1
  bic v2.4h, #1
  bic v3.4h, #1
  bic v4.4h, #1
  bic v5.4h, #1
  bic v6.4h, #1
  bic v7.4h, #1
  bic v8.4h, #1
  bic v9.4h, #1
  bic v10.4h, #1
  bic v11.4h, #1
  bic v12.4h, #1
  bic v13.4h, #1
  bic v14.4h, #1
  bic v15.4h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	12	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	21	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	0	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	21	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	24	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	135	25	160100	100	160000	100	160000	500	1120016	0	0	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40089	40039
160204	40038	300	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	12	9	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	6	0	40	25	160100	100	160000	100	160000	500	1120016	0	0	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	10	15	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	9	12	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	0	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40040	300	0	0	0	1007	25	160010	10	160000	10	160000	50	1120016	1	1	0	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	1	1	41	16	2	1	1	13	15	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	1071	25	160010	10	160000	10	160000	50	1120016	1	1	5	40068	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	13	16	2	1	1	15	13	40035	20	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	320	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	15	16	2	1	1	12	14	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	364	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	14	16	2	1	1	15	12	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	414	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	14	16	2	1	1	16	9	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	368	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	13	16	2	1	1	15	14	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	364	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	15	16	2	1	1	13	13	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	3	0	341	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	15	16	2	1	1	15	15	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	388	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	15	16	2	1	1	15	14	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	410	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	4	1	14	16	2	1	1	16	15	40035	20	8	160000	10	40039	40039	40039	40039	40039

BIC (vector, immediate, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations