Firestorm: BIC (vector, immediate, 4S) measurements

Code:

  bic v0.4s, #1

Initialization

  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	82	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	1	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	1686	25	1000	1000	1000	264521	2018	2037	2037	1571	3	1895	1000	1000	1000	2037	2037	1	1	1001	1000	3	0	73	1	16	1	1	1786	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bic v0.4s, #1

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	7	18741	10100	200	10000	200	10000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19864	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	1597	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	1	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20054	20037	20037	18428	7	18740	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2851313	1	20018	20037	20037	18428	7	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	4	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10114	106	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19801	0	10000	100	20038	20038	20182	20038	20038
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	6	18741	10100	200	10008	200	10008	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	5	24	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20085	18447	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	212	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	251	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	187	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	2	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	9	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	10000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	0	10000	10	20038	20038	20038	20038	20038

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  bic v0.4s, #1
  movi v1.16b, 0
  bic v1.4s, #1
  movi v2.16b, 0
  bic v2.4s, #1
  movi v3.16b, 0
  bic v3.4s, #1
  movi v4.16b, 0
  bic v4.4s, #1
  movi v5.16b, 0
  bic v5.4s, #1
  movi v6.16b, 0
  bic v6.4s, #1
  movi v7.16b, 0
  bic v7.4s, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	60	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10119	0	0	10	16	8	4	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10119	0	0	9	16	4	8	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	3	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10119	0	0	8	16	8	8	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	18	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10118	0	0	9	16	8	9	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	6	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10119	0	0	4	16	9	9	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	27	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10119	0	0	9	16	11	10	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	2	0	0	10141	0	0	9	16	8	8	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	3	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10119	0	0	8	16	8	9	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	3	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10119	0	0	8	16	9	9	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	9	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	80000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10119	0	0	9	16	9	9	20060	0	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20082	150	0	3	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20059	20050	3	21	80012	20	80000	20	80000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	10034	8	4	1	23	34	4	2	2	11	23	20047	2	40	2	160000	10	20060	20051	20051	20060	20060
160024	20059	150	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20059	3	21	80012	20	80000	20	80000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10046	8	5	1	22	25	2	1	1	22	22	20047	2	20	1	160000	10	20060	20051	20051	20051	20051
160024	20050	150	0	507	44	27	80012	12	80000	12	80000	62	640000	0	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	80000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10046	8	5	1	22	34	2	1	1	21	8	20047	2	20	2	160000	10	20060	20051	20051	20051	20051
160024	20059	150	0	375	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20059	3	21	80012	20	80000	20	80000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	10046	8	5	1	10	25	2	1	1	22	11	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	6	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	80000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10034	8	5	2	22	34	2	1	1	10	22	20056	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	3	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20059	20050	3	21	80012	20	80000	20	80000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	10046	8	5	1	22	25	2	1	1	10	22	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20059	150	0	9	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	80000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10045	8	5	1	21	25	2	1	1	22	8	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	12	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	80000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10048	8	5	1	22	34	2	1	1	10	22	20047	2	40	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	492	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	80000	20050	20179	1	1	160021	10	9	10	10	160000	10	0	0	10045	8	5	1	19	25	2	1	1	22	8	20047	2	20	1	160000	10	20051	20051	20051	20060	20051
160024	20050	150	1	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	80000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10045	8	5	1	22	25	2	1	1	23	23	20047	2	20	1	160000	10	20051	20051	20051	20051	20051

Test 4: throughput

Count: 16

Code:

  bic v0.4s, #1
  bic v1.4s, #1
  bic v2.4s, #1
  bic v3.4s, #1
  bic v4.4s, #1
  bic v5.4s, #1
  bic v6.4s, #1
  bic v7.4s, #1
  bic v8.4s, #1
  bic v9.4s, #1
  bic v10.4s, #1
  bic v11.4s, #1
  bic v12.4s, #1
  bic v13.4s, #1
  bic v14.4s, #1
  bic v15.4s, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40038	300	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	2	40035	0	160000	100	40039	40039	40088	40048	40039
160204	40038	300	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	2	16	2	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	2	0	10110	1	16	2	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	515	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	3	3	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	2	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	2	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	6	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	2	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	0	40	25	160100	100	160000	100	160000	500	1120016	1	40019	40038	40038	19973	3	19996	160100	200	160000	200	160000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	2	16	2	1	40035	0	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40050	300	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	0	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	2	1	4	17	2	1	1	4	3	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	51	25	160010	10	160000	10	160000	50	1120016	0	1	5	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	3	2	5	17	4	2	2	3	4	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	5	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	5	17	2	1	1	5	5	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	27	51	25	160010	10	160000	10	160000	50	1120016	0	1	5	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	3	2	3	17	4	2	2	4	3	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	51	25	160010	10	160000	10	160000	50	1120016	0	1	5	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	3	2	4	17	4	2	2	4	4	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	45	25	160010	10	160000	10	160000	50	1120016	1	1	0	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	3	2	5	17	4	2	2	5	5	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	51	49	160010	10	160000	10	160000	50	1120016	0	1	5	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	3	2	5	17	4	2	2	5	5	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	51	25	160010	10	160000	10	160000	50	1120016	0	1	5	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	11	1	2	3	17	4	2	2	4	4	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	30	51	25	160010	10	160000	10	160000	50	1120016	0	1	0	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	8	3	2	3	17	4	2	2	5	3	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	520	25	160010	10	160000	10	160000	50	1120016	0	0	0	40019	40038	40038	19989	3	20011	160010	20	160000	20	160000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	3	2	3	17	4	2	2	3	4	40035	40	16	160000	10	40039	40039	40039	40039	40039

BIC (vector, immediate, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations