Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BIC (vector, immediate, 8H)

Test 1: uops

Code:

  bic v0.8h, #1
  movi v0.16b, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037160611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037160611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
10042037150611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
1004203715396116862510001000100026452112018203720371571318951000100010002037203711100110001573116111786100020382038203820382038
10042037150611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038

Test 2: Latency 1->1

Code:

  bic v0.8h, #1
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968625101001001000010010000500284752112001820037200371842807187401010020010008200100002003720037111020110099100100100001000001117222242219787100001002003820038200382003820038
1020420037150000971968625101001001000010010000500284752112001820037200371840906187331010020010000200100002003720037111020110099100100100001000001117222242219787100001002003820038200382003820038
1020420037150000971968625101001001000010010000500284752112001820037200371840906187331010020010000200100002008420037111020110099100100100001000021117222242219787100001002003820038200382003820038
1020420037150001971968625101001001000010010000500284752112001820037200371840906187331010020010000200100002003720037111020110099100100100001000001117222242219787100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842806187411010020010008200100002003720037111020110099100100100001000001117222242219787100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842807187401010020010008200100082003720037111020110099100100100001000001117170160019801100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842807187401010020010008200100082003720037111020110099100100100001000001117180160019800100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842806187401010020210008200101742003720180211020110099100100100001002001117170160019801100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842807187411010020010008200100082003720037111020110099100100100001000001117170160019801100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752112001820037200371842806187401010020010008200100082003720037111020110099100100100001000001117180160019801100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715011002110196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001011300644101610101978610000102003820038200382003820038
1002420037150110026819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000644121610101978610000102003820038200382003820038
100242003715011002681968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000064461610101978610000102003820038200382003820038
10024200371501100268196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000406445161051978610000102003820038200382003820038
1002420037150110026819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000644101611101978610000102003820038200382003820038
1002420037150110026819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000644101611101978610000102003820038200382003820038
10025200371501100254319686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000644101610101978610000102003820038200382003820038
1002420037150110026819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000644101610101978610000102003820038200382003820038
1002420037150110026819686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100000644101610101978610000102003820038200382003820038
100242003715011002681968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000064451610101978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  movi v0.16b, 0
  bic v0.8h, #1
  movi v1.16b, 0
  bic v1.8h, #1
  movi v2.16b, 0
  bic v2.8h, #1
  movi v3.16b, 0
  bic v3.8h, #1
  movi v4.16b, 0
  bic v4.8h, #1
  movi v5.16b, 0
  bic v5.8h, #1
  movi v6.16b, 0
  bic v6.8h, #1
  movi v7.16b, 0
  bic v7.8h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042008915003825801001008000010080000500640000120044200632006332180100200800002008000020063200631116020110099100100160000100000010111116112006001600001002006420064200642006420064
1602042006315003825801001008000010080000500640000120044200632006332180100200800002008000020063200631116020110099100100160000100000010111116112006001600001002006420064200642006420064
1602042006315103825801001008000010080000500640000020044200632006332180100200800002008000020063200631116020110099100100160000100000310111116112006001600001002006420064200642006420064
1602042006315003825801001008000010080000500640000020044200632006332180100200800002008000020063200631116020110099100100160000100000010111116112006001600001002006420064200642006420064
1602042006315003825801001008000010080000500640000120044200632006332180100200800002008000020063200631116020110099100100160000100000010111116112006001600001002006420064200642006420064
160204200631500382580100100800001008000050064000012004420063200633218010020080000200800002006320063111602011009910010016000010004309010111116112006001600001002006420064200642006420064
16020420063150038258010010080000100800005006400001200442006320063321801002008000020080000200632006311160201100991001001600001000106101111162220253191600001002006420064200642006420064
1602042006315003825801001008000010080000500640000120044200632006332180100200800002008000020063200631116020110099100100160000100010910111116112006001600001002006420064200642006420064
16020420063150038258010010080000100800005006400001200442006320063321801002008000020080000200632006311160201100991001001600001000100010111116112006001600001002006420064200642006420168
1602042006315003825801001008000010080000500640000120044200632006332180100200800002008000020063200631116020110099100100160000100000010111116112006001600001002006420064200642006420064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200661500012144278001212800001280000626400001152003120050200503218001220800002080000200502005011160021109101016000010031003083155721146200472201160000102005820051200512005120060
160024200501500018144278001212800001280000626400001152003120050200503218001220800002080000200502005011160021109101016000010001002883142521174200472201160000102005120051200512005120051
16002420050150000172278001212800001280000626400001152003120050200503218001220800002080000200502005011160021109101016000010001003231162521164200472201160000102005120051200512005120051
16002420050150000144278001212800001280000626400001102003120050200503218001220800002080000200502005011160021109101016000010001003581162521166200472201160000102005120051200512005120051
16002420059150000150278001212800001280000626400001152003120050200503218001220800002080000200502005011160021109101016000010101003081192521166200472201160000102005120051200512005120051
16002420050150000144278001212800001280000626400001152003120050200503218001220800002080000200592005911160021109101016000010001003162262542266200562402160000102005120051200512005120051
16002420050150003314427800121280000128000062640000110201342005020050321800122080000208000020050200501116002110910101600001034010032111192521189200472201160000102005120051200512005120051
16002420050150000144278001212800001280000626400001152003120050200503218001220800002080000200502005011160021109101016000010001003233162521156200472201160000102005120051200512005120051
16002420050150000184278001212800001280000626400001152003120050200503218001220800002080000200502005011160021109101016000010301003381182521198200472201160000102005120051200512005120051
160024200501500001442980012128000012800006264000011520031200502005032180012208000020800002005020050111600211091010160000103701003383192521198200472201160000102005120051203622005120060

Test 4: throughput

Count: 16

Code:

  bic v0.8h, #1
  bic v1.8h, #1
  bic v2.8h, #1
  bic v3.8h, #1
  bic v4.8h, #1
  bic v5.8h, #1
  bic v6.8h, #1
  bic v7.8h, #1
  bic v8.8h, #1
  bic v9.8h, #1
  bic v10.8h, #1
  bic v11.8h, #1
  bic v12.8h, #1
  bic v13.8h, #1
  bic v14.8h, #1
  bic v15.8h, #1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400583000000004025160100100160000100160000500112001611400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110121622400351600001004003940039400394003940039
16020440038300000000109325160100100160000100160000500112001611400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110021622400351600001004003940039400394003940039
160204400382990000004025160100100160000100160000536112001611400194003840038199733199961601002001600002001601364003840038111602011009910010016000010000010110121622400351600001004003940039400394003940039
160204400383000000004025160100100160000100160000500112001601400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110121622400351600001004003940039400394003940039
160204400383000000004025160100100160000100160000500112001611400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110121622400351600001004003940039400394003940039
1602044003830000000023025160100100160000100160000500112001601400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110121622400351600001004003940039400394003940039
160204400383000000004025160100100160000100160000500112001611400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110021622400351600001004003940039400394003940039
160204400383000000004025160100100160000100160000500112001601400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110021622400351600001004003940039400394003940039
160204400383000000004025160100100160000100160000500112001601400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110121622400351600001004003940039400394003940039
160204400383000000004025160100100160000100160000500112001601400194003840038199733199961601002001600002001600004003840038111602011009910010016000010000010110021622400351600001004003940039400394003940039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400473001000000045251600101016000010160000501120016114001940038400381999603200181600102016000020160000400384003811160021109101016000010000000000100223111216411107400350208160000104003940039400394003940039
160024400383000000000093625160010101600001016000050112001611400194003840038199960320018160010201600002016000040038400381116002110910101600001000000000010022311716212810400350208160000104003940093400894003940039
1600244003830000000015045251600101016000010160000501120016114001940038400381999673200181600102016000020160000400384003811160021109101016000010000040000100223111016211710400350208160000104003940039400394003940039
16002440038300000000004525160010101600001016000050112001611400194003840038199960320018160010201600002016000040038400381116002110910101600001000001000010022311716211107400350208160000104003940039400394003940039
16002440038300000000004525160010101600001016000050112001611400194003840038199960320018160010201600002016000040038400381116002110910101600001000000000010022311716211107400350208160000104003940039400394003940039
160024400383000000000045251600101016000010160000501120016114001940038400381999603200181600102016000020160000400384003811160021109101016000010000000000100223111016211710400350208160000104003940039400394003940039
1600244003829900000030045251600101016000010160000501120016214001940038400381999603200181600102016000020160000400384003811160021109101016000010000000000100223111016211108400350208160000104003940039402424003940039
16002440038300000000004525160010101600001016000050112001611400194003840038199920320018160010201600002016000040038400381116002110910101600001000000000010022311816211810400350208160000104003940039400394003940039
160024400383000000000045251600101016000010160000501120016114001940038400381999603200181600102016000020160000400384003811160021109101016000010000000000100223111016211107400350208160000104003940039400394003940039
160024400383000000000045251600101016000010160000501120016114001940038400381999603200181600102016000020160000400384003811160021109101016000010000000000100223111016211107400350208160000104003940039400394003940039