Firestorm: BIF (vector, 16B) measurements

Code:

  bif v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bif v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	24	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	9	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	3	0	0	640	4	24	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	12	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	0	0	640	3	16	5	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	2	0	0	0	640	4	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  bif v0.16b, v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	3	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	78	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	2	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	8	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	9	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	81	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	441	19687	25	10010	10	10000	10	10000	60	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	2	16	2	2	19785	0	10000	10	20122	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	60	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	7	3	18767	10010	20	10000	20	30000	20037	20084	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	0	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10012	12	10000	12	10000	60	2847680	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	132	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  bif v0.16b, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	159	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	12	573	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	204	30498	20179	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	155	0	61	19687	82	10100	100	10000	100	10000	565	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30492	20086	20037	1	1	10201	100	99	100	100	10000	100	2	0	0	734	1	16	1	1	19859	10000	100	20038	20038	20038	20038	20038
10204	20037	150	12	103	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19676	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	4	0	710	1	16	1	1	19791	10000	100	20085	20038	20038	20085	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	99	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	105	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	9	982	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	9	103	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10172	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10025	20037	150	117	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	84	19676	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	84	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	4	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	103	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	4	3	19785	3	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	84	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	4	3	19785	0	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bif v0.16b, v8.16b, v9.16b
  movi v1.16b, 0
  bif v1.16b, v8.16b, v9.16b
  movi v2.16b, 0
  bif v2.16b, v8.16b, v9.16b
  movi v3.16b, 0
  bif v3.16b, v8.16b, v9.16b
  movi v4.16b, 0
  bif v4.16b, v8.16b, v9.16b
  movi v5.16b, 0
  bif v5.16b, v8.16b, v9.16b
  movi v6.16b, 0
  bif v6.16b, v8.16b, v9.16b
  movi v7.16b, 0
  bif v7.16b, v8.16b, v9.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20087	150	0	229	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10113	1	16	3	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	2	16	2	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	147	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	17	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10112	1	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	418	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	2	3	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	2	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	2	16	1	1	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	103	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	2	2	20060	0	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20071	150	0	0	0	0	0	0	0	113	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10027	8	2	1	5	34	4	1	1	10	4	20047	2	20	1	160000	10	20060	20060	20060	20060	20060
160024	20050	150	0	0	0	0	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10030	11	5	2	4	34	4	2	2	11	3	20047	2	20	1	160000	10	20051	20051	20051	20060	20051
160024	20050	150	0	0	0	0	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10030	11	5	2	3	34	4	2	2	7	4	20047	2	20	1	160000	10	20051	20051	20051	20060	20060
160024	20050	151	0	0	0	0	0	0	0	723	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20059	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10026	8	4	1	4	25	2	1	1	12	4	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	0	0	44	29	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20222	20063	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10027	8	4	1	4	25	4	1	1	4	3	20047	2	20	1	160000	10	20051	20060	20060	20051	20051
160024	20050	150	0	0	0	0	0	0	0	86	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20219	20063	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10027	8	3	2	3	25	2	2	1	3	4	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	12	0	67	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20235	20217	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10027	8	3	1	4	25	2	2	1	4	3	20056	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20203	20063	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10026	8	3	1	3	25	2	1	1	4	4	20056	2	40	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20212	20063	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10027	8	4	2	3	25	2	2	1	4	3	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	20059	20059	3	21	80012	20	80000	20	240000	20215	20063	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10027	8	4	1	4	25	2	2	1	3	4	20047	2	20	1	160000	10	20051	20051	20051	20051	20051

Test 6: throughput

Count: 16

Code:

  bif v0.16b, v16.16b, v17.16b
  bif v1.16b, v16.16b, v17.16b
  bif v2.16b, v16.16b, v17.16b
  bif v3.16b, v16.16b, v17.16b
  bif v4.16b, v16.16b, v17.16b
  bif v5.16b, v16.16b, v17.16b
  bif v6.16b, v16.16b, v17.16b
  bif v7.16b, v16.16b, v17.16b
  bif v8.16b, v16.16b, v17.16b
  bif v9.16b, v16.16b, v17.16b
  bif v10.16b, v16.16b, v17.16b
  bif v11.16b, v16.16b, v17.16b
  bif v12.16b, v16.16b, v17.16b
  bif v13.16b, v16.16b, v17.16b
  bif v14.16b, v16.16b, v17.16b
  bif v15.16b, v16.16b, v17.16b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	0	0	0	18	40	0	25	160206	100	160106	100	160000	500	1280000	1	40093	40112	40038	19973	0	3	19996	160100	200	160000	200	480000	40056	40038	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40035	0	160000	100	40039	40189	40039	40039	40039
160204	40188	299	0	0	0	0	40	0	25	160100	100	160036	100	160000	500	1280000	1	40019	40038	40085	19994	0	3	20043	160100	200	160000	200	480000	40075	40039	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40082	0	160000	100	40113	40039	40113	40039	40039
160204	40038	300	0	0	0	0	40	382	25	160100	100	160000	100	160000	500	5534613	0	40019	40038	40038	19973	0	3	20070	160100	200	160000	200	480000	40038	40057	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40189
160204	40038	300	0	0	0	0	40	382	25	160100	100	160000	100	160000	500	1280000	0	40019	40038	40038	19973	13	3	20021	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40185	0	160000	100	40039	40039	40039	40189	40039
160204	40237	300	0	0	15	0	61	0	25	160100	100	160000	100	160000	500	1280000	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40109	0	160000	100	40039	40039	40039	40039	40039
160204	40188	300	0	0	0	0	61	650	25	160100	100	160000	100	160000	500	1280000	0	40019	40055	40038	20093	3	3	20023	160100	200	160000	200	480000	40064	40063	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40189	40039	40039
160204	40038	300	0	0	0	0	40	382	25	160100	100	160000	100	160000	500	1280000	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	480000	40114	40038	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	2	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	301	0	0	0	73	61	0	25	160100	100	160000	100	160000	500	1280000	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	480000	40039	40057	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40035	0	160000	100	40039	40113	40039	40113	40039
160204	40038	301	0	0	0	209	40	149	25	160100	100	160000	100	160000	500	3692954	0	40019	40038	40188	20093	0	3	19996	160100	200	160000	200	480000	40188	40038	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40065	301	0	0	0	0	40	0	25	160100	100	160106	100	160000	500	1280000	0	40019	40038	40038	19973	0	3	20070	160100	200	160000	200	480000	40038	40188	1	1	160201	100	99	100	100	160000	100	0	0	10110	1	16	1	1	40035	0	160000	100	40039	40039	40039	40189	40189

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40092	301	0	0	0	45	0	25	160116	10	160106	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	30	11	16	2	1	1	4	2	40035	20	8	160000	10	40113	40039	40039	40039	40067
160024	40038	300	0	0	0	45	0	25	160010	10	160106	10	160000	50	1280000	1	1	40019	40038	40075	20037	0	3	20018	160010	20	160000	20	480000	40056	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	42	3	16	2	1	1	2	4	40035	20	8	160000	10	40039	40067	40039	40039	40076
160024	40075	299	0	12	0	67	0	25	160116	10	160000	10	160000	50	4728951	1	1	40056	40112	40038	19996	13	3	20055	160010	20	160000	20	480000	40038	40075	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	31	4	16	2	1	1	2	4	40035	20	8	160000	10	40039	40113	40039	40064	40039
160024	40038	300	0	0	0	67	0	25	160010	10	160000	10	160000	50	1280000	1	1	40056	40066	40038	19996	0	3	20055	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	12	27	10022	3	1	30	4	16	2	1	1	4	4	40072	20	8	160000	10	40076	40039	40039	40039	40113
160024	40112	300	0	0	0	45	0	25	160010	10	160000	10	160000	50	5438340	1	1	40056	40038	40038	20006	0	25	20045	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	31	5	16	2	1	1	4	6	40035	20	8	160000	10	40039	40076	40039	40113	40039
160024	40038	300	0	0	76	710	0	25	160010	10	160045	10	160000	50	1280000	1	1	40056	40038	40075	20006	13	3	20055	160010	20	160000	20	480000	40038	40075	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	33	4	16	2	1	1	2	4	40035	20	8	160000	10	40076	40039	40076	40039	40083
160024	40038	300	0	0	45	67	39	25	160060	10	160023	10	160000	50	1280000	1	1	40019	40075	40038	19996	0	3	20018	160010	20	160000	20	480000	40056	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	6	1	29	4	16	2	1	1	2	4	40035	20	8	160000	10	40064	40039	40076	40039	40039
160024	40038	300	0	0	0	45	149	25	160011	10	160076	10	160000	50	1280000	1	1	40019	40038	40038	20006	0	3	20018	160010	20	160000	20	480000	40074	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	26	4	41	2	1	1	5	2	40035	20	8	160000	10	40039	40076	40039	40040	40039
160024	40038	300	0	0	0	45	67	25	160010	10	160000	10	160000	50	4728951	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40112	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	29	4	16	2	1	1	4	2	40035	20	8	160000	10	40083	40039	40113	40039	40039
160024	40038	300	0	0	0	67	77	25	160010	10	160076	10	160000	50	5438340	1	1	40019	40038	40075	20037	13	3	20092	160010	20	160000	20	480000	40038	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	29	4	16	2	1	1	2	4	40035	20	8	160000	10	40039	40039	40076	40039	40039

BIF (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations