Firestorm: BIF (vector, 8B) measurements

Code:

  bif v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	3	72	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	1	0	3	72	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	3	72	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	3	72	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	7	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	3	72	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	9	3	72	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	9	3	72	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	13	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	3	72	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	3	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	3	72	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	3	72	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	79	4	1	16	1	1	3	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bif v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	346	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	710	1	0	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	84	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10332	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	3	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	1	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	84	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	1	0	0	0	0	0	124	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	662	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	82	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	4	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19853	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	0	0	0	0	0	251	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  bif v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	655	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	726	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20084	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	15	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	9	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	6	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	11	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20084
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	366	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	411	0	156	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	2	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	6	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18805	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20085	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	6	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  bif v0.8b, v1.8b, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	1	0	1	72	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20086	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	69	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	9	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	36	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	4	25	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	3	0	12	638	19687	25	10100	100	10048	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	15	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	15	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	6	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20132	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	15	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	24	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	4	16	4	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	4	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	15	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	4	16	4	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	78	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	4	16	4	4	19785	10000	10	20085	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	15	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	4	3	19785	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bif v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  bif v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  bif v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  bif v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  bif v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  bif v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  bif v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  bif v7.8b, v8.8b, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	151	51	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10112	1	16	1	2	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	3	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	2	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	125	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	2	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	36	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	3	16	1	2	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	36	228	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	2	2	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	36	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	3	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	15	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10145	1	16	2	2	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	36	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10113	1	16	2	3	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	36	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	2	16	2	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	36	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	2	20060	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20056	150	0	0	0	0	18	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80100	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	1	1	2	20	2	1	1	2	3	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	151	0	0	0	0	0	0	0	157	63	80113	13	80101	12	80000	62	640000	0	1	20093	20287	20049	3	21	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10028	6	2	2	2	24	4	2	2	3	3	20046	2	30	160000	10	20150	20149	20050	20050	20050
160024	20049	150	0	0	0	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20049	3	21	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	6	2	2	3	20	4	2	2	3	2	20042	2	30	160000	10	20050	20046	20050	20046	20050
160024	20049	150	0	0	0	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	0	1	20026	20049	20045	3	21	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	6	2	2	2	24	4	2	2	2	3	20046	2	30	160000	10	20046	20050	20050	20046	20050
160024	20045	150	0	0	0	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20049	3	21	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10029	6	2	2	3	24	4	2	1	3	4	20046	2	30	160000	10	20050	20050	20050	20050	20050
160024	20049	150	0	0	0	0	0	0	0	50	25	80012	12	80000	12	80000	62	640000	0	1	20026	20049	20049	3	21	80012	20	80000	20	240000	20049	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10028	6	2	2	3	24	4	2	1	3	3	20046	2	30	160000	10	20050	20050	20050	20046	20050
160024	20049	150	0	0	0	0	12	0	0	50	25	80012	12	80000	12	80000	62	640000	1	1	20030	20049	20049	3	21	80012	20	80000	20	240000	20049	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10026	3	2	2	3	20	4	2	1	3	3	20046	2	30	160000	10	20050	20046	20046	20050	20046
160024	20049	150	0	0	0	0	0	0	0	44	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20049	3	21	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	10029	6	2	2	2	24	4	2	2	2	3	20046	2	30	160000	10	20050	20050	20050	20050	20050
160024	20049	150	0	0	0	0	12	0	0	50	25	80012	12	80000	12	80000	62	640000	0	1	20030	20049	20045	3	21	80012	20	80000	20	240000	20049	20045	1	1	160021	10	9	10	10	160000	10	0	0	1	0	3	10028	6	1	2	3	24	4	2	2	3	2	20046	2	30	160000	10	20050	20046	20050	20050	20050
160024	20138	150	0	0	1	0	18	0	0	92	25	80012	12	80000	12	80000	62	640800	1	1	20026	20049	20049	3	21	80112	20	80000	20	240000	20049	20045	2	1	160021	10	9	10	10	160000	10	4	0	1	0	488	10027	3	1	1	4	20	2	1	1	3	3	20042	2	15	160000	10	20046	20046	20046	20046	20046

Test 6: throughput

Count: 16

Code:

  bif v0.8b, v16.8b, v17.8b
  bif v1.8b, v16.8b, v17.8b
  bif v2.8b, v16.8b, v17.8b
  bif v3.8b, v16.8b, v17.8b
  bif v4.8b, v16.8b, v17.8b
  bif v5.8b, v16.8b, v17.8b
  bif v6.8b, v16.8b, v17.8b
  bif v7.8b, v16.8b, v17.8b
  bif v8.8b, v16.8b, v17.8b
  bif v9.8b, v16.8b, v17.8b
  bif v10.8b, v16.8b, v17.8b
  bif v11.8b, v16.8b, v17.8b
  bif v12.8b, v16.8b, v17.8b
  bif v13.8b, v16.8b, v17.8b
  bif v14.8b, v16.8b, v17.8b
  bif v15.8b, v16.8b, v17.8b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	0	27	0	23	0	61	0	25	160101	100	160001	100	160000	500	1280000	1	40019	40038	40039	19974	0	3	20036	160100	200	160000	200	480000	40038	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40149	160000	100	40039	40040	40039	40040	40039
160204	40039	300	0	0	0	0	141	0	516	10	25	160127	100	160027	100	160000	500	4437926	0	40038	40038	40107	19973	0	3	19996	160100	200	160000	200	480000	40038	40073	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40059	160000	100	40039	40039	40063	40063	40039
160204	40062	300	0	0	51	0	1	0	126	0	25	160100	100	160000	100	160000	500	4437926	1	40019	40038	40417	19973	0	3	20048	160100	200	160000	200	480000	40289	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	12	0	10110	1	16	1	1	40036	160000	100	40063	40063	40063	40063	40039
160204	40144	299	0	0	0	0	0	0	40	0	25	160131	100	160000	100	160000	500	1319998	1	40019	40038	40289	19973	0	3	20036	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	29	1	1	40036	160000	100	40039	40079	40040	40039	40040
160204	40039	299	0	0	0	0	27	0	61	10	25	160100	100	160000	100	160000	500	2462584	0	40048	40038	40078	19973	0	3	19996	160100	200	160000	200	480000	40038	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40072	160000	100	40040	40039	40040	40039	40056
160204	40038	300	0	0	0	0	26	0	61	0	25	160100	100	160338	100	160000	500	1280000	1	40044	40038	40039	19986	0	3	19997	160100	200	160000	200	480000	40039	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40075	160000	100	40079	40040	40039	40040	40040
160204	40090	299	0	0	0	0	167	0	103	0	25	160127	100	160027	100	160000	500	5483355	1	40270	40038	40038	20043	11	3	20020	160100	200	160000	200	480000	40064	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40141	160000	100	40039	40290	40039	40290	40039
160204	40038	300	0	0	0	0	0	0	84	0	25	160101	100	160001	100	160000	500	1280000	0	40133	40039	40439	19973	0	3	20036	160100	200	160000	200	480000	40038	40039	1	1	160201	100	99	100	100	160000	100	0	1	0	9	0	10110	1	16	1	1	40107	160000	100	40039	40145	40290	40039	40039
160204	40144	300	0	0	0	0	23	0	40	0	25	160100	100	160001	100	160000	500	5435282	1	40059	40038	40039	19973	0	3	19997	160100	200	160000	200	480000	40078	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40075	160000	100	40040	40039	40079	40040	40039
160204	40038	299	0	0	0	0	1	0	61	10	25	160123	100	160000	100	160000	500	1319998	0	40044	40078	40078	19973	0	3	19997	160100	200	160000	200	480000	40039	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40039	40040	40039	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40083	301	0	0	0	67	110	25	160033	10	160000	10	160000	50	5402633	1	1	40020	40099	40099	20031	0	3	20018	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	4	6	0	10022	3	1	1	6	16	2	1	1	3	9	40096	20	9	160000	10	40100	40100	40149	40040	40039
160024	40099	300	0	0	0	216	110	25	160092	10	160082	10	160000	50	1280000	1	1	40080	40099	40099	20031	0	3	20018	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	2	1	9	16	2	1	1	9	3	40096	20	7	160000	10	40100	40039	40039	40100	40100
160024	40099	300	0	0	82	45	0	25	160092	10	160082	10	160000	50	5402633	1	1	40080	40038	40099	20031	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	3	16	2	1	1	3	9	40035	20	9	160000	10	40100	40058	40039	40100	40149
160024	40099	300	0	0	82	45	110	25	160010	10	160082	10	160000	50	1280000	1	1	40019	40099	40148	19996	0	3	20079	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	11	16	2	1	1	9	3	40096	20	8	160000	10	40039	40100	40100	40100	40100
160024	40038	299	0	0	0	45	110	25	160010	10	160000	10	160000	50	3997424	1	1	40080	40038	40038	20031	0	3	20079	160010	20	160000	20	480000	40038	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	5	16	2	1	1	3	9	40096	20	9	160000	10	40100	40100	40149	40040	40100
160024	40099	300	0	0	82	67	110	25	160011	10	160082	10	160000	50	5402633	1	1	40080	40099	40099	20031	0	3	20128	160010	20	160000	20	480000	40099	40148	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	9	16	2	1	1	6	9	40096	20	8	160000	10	40100	40100	40100	40040	40100
160024	40154	300	0	0	82	67	0	25	160092	10	160023	10	160000	50	1280000	1	1	40080	40038	40038	20031	0	3	20018	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	9	16	2	1	1	5	3	40096	20	9	160000	10	40100	40100	40100	40039	40149
160024	40099	301	0	0	0	542	0	25	160092	10	160000	10	160000	50	5402633	1	1	40080	40099	40057	19996	0	3	20018	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	465	0	10022	3	1	1	9	16	2	1	1	9	9	40096	20	9	160000	10	40100	40100	40100	40100	40100
160024	40099	300	0	0	82	46	110	25	160092	10	160082	10	160000	50	5402633	1	1	40080	40090	40099	20031	0	3	20079	160010	20	160000	20	480000	40099	40099	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	3	16	2	1	1	3	5	40096	20	9	160000	10	40100	40100	40100	40100	40039
160024	40038	300	0	0	82	67	110	25	160092	10	160001	10	160000	50	1280000	1	1	40080	40099	40057	20031	0	3	20079	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	5	16	2	1	1	5	5	40096	20	8	160000	10	40100	40100	40100	40149	40149

BIF (vector, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations