Firestorm: BIT (vector, 16B) measurements

Code:

  bit v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	15	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	105	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1152	1168	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	105	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bit v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	399	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20086	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	136	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18765	10100	200	10000	200	30000	20037	20037	1	1	10202	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	72	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	145	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	6	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	6	0	61	19687	25	10100	100	10000	100	10000	500	2847680	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	712	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	60	0	0	66	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	6	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	9	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	288	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	195	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  bit v0.16b, v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	61	19676	25	10100	100	10000	100	10000	644	2847680	0	20018	20085	20085	18422	3	18745	10100	204	10000	200	30000	20037	20084	2	1	10201	100	99	100	100	10000	100	0	0	0	0	2071	0	710	1	16	1	2	19791	0	10000	100	20038	20038	20085	20038	20038
10204	20132	150	0	18	0	103	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	12	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	21	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18426	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	15	0	103	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20230	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20181	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	2	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	264	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	231	82	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2093	640	3	16	4	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20084	150	189	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	198	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	309	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	120	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	6	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	3	4	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	3	19785	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  bit v0.16b, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	36	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20085	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	82	19687	25	10137	100	10000	100	10000	522	2847680	1	20018	20074	20037	18422	3	18745	10100	200	10168	204	30000	20037	20037	2	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	441	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	15	0	103	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19825	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	9	88	61	19687	62	10130	100	10000	100	10000	500	2847680	1	20018	20085	20037	18422	3	18782	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	156	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	111	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	1	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	536	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	300	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	291	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	3	3	19785	0	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bit v0.16b, v8.16b, v9.16b
  movi v1.16b, 0
  bit v1.16b, v8.16b, v9.16b
  movi v2.16b, 0
  bit v2.16b, v8.16b, v9.16b
  movi v3.16b, 0
  bit v3.16b, v8.16b, v9.16b
  movi v4.16b, 0
  bit v4.16b, v8.16b, v9.16b
  movi v5.16b, 0
  bit v5.16b, v8.16b, v9.16b
  movi v6.16b, 0
  bit v6.16b, v8.16b, v9.16b
  movi v7.16b, 0
  bit v7.16b, v8.16b, v9.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	21	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	21	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	273	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	219	38	25	80100	100	80000	100	80000	644	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	2	2	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	396	38	25	80100	100	80000	100	80000	500	640000	1	20044	0	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20061	150	0	0	1	0	0	0	56	27	80012	12	80000	12	80000	62	640000	1	1	5	20040	0	20050	20059	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10037	11	2	1	17	25	2	1	1	14	14	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	2	0	0	0	119	27	80012	12	80000	12	80000	62	640000	0	1	5	20031	0	20059	20059	3	21	80012	20	80000	20	240000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	10042	11	3	2	16	34	4	2	2	16	16	20056	2	20	2	160000	10	20060	20060	20060	20051	20060
160024	20059	156	1	0	1	0	0	0	56	29	80012	12	80000	12	80000	62	640000	0	1	5	20031	0	20059	20050	3	21	80012	20	80000	20	240000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	10042	11	3	2	16	34	4	1	2	15	15	20047	2	40	2	160000	10	20060	20060	20051	20060	20060
160024	20059	150	1	0	1	0	0	0	56	27	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20050	20050	3	21	80012	20	80000	20	240000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	10041	11	3	1	15	34	4	2	1	8	15	20047	2	40	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	2	0	0	0	0	0	62	27	80012	12	80000	12	80000	62	640000	0	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10038	11	2	1	16	34	4	1	1	15	14	20056	2	20	1	160000	10	20060	20051	20051	20051	20060
160024	20050	150	2	0	2	1	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20031	0	20050	20059	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10039	8	2	1	15	25	2	1	1	15	15	20047	2	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	1	0	2	0	0	0	50	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20050	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10038	8	2	1	17	34	2	1	2	17	15	20056	2	20	1	160000	10	20051	20051	20060	20051	20060
160024	20059	150	1	0	0	0	0	0	68	29	80012	12	80000	12	80000	62	640000	1	1	5	20031	0	20050	20216	20	21	80012	20	80000	20	240000	20059	20059	1	1	160021	10	9	10	10	160000	10	1	6	10041	11	2	2	18	34	4	1	2	17	16	20112	2	40	1	160000	10	20060	20131	20060	20138	20112
160024	20146	151	3	0	3	0	0	0	62	27	80012	12	80000	12	80000	62	640000	1	1	5	20040	0	20050	20059	3	21	80012	20	80000	20	240000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10044	11	3	2	17	34	4	1	2	18	17	20047	2	40	1	160000	10	20060	20051	20060	20051	20060
160024	20059	150	1	0	1	0	21	0	44	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	0	20059	20059	3	21	80012	20	80000	20	240000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	3	10041	8	3	2	15	25	2	1	2	16	16	20056	2	40	1	160000	10	20060	20051	20051	20051	20060

Test 6: throughput

Count: 16

Code:

  bit v0.16b, v16.16b, v17.16b
  bit v1.16b, v16.16b, v17.16b
  bit v2.16b, v16.16b, v17.16b
  bit v3.16b, v16.16b, v17.16b
  bit v4.16b, v16.16b, v17.16b
  bit v5.16b, v16.16b, v17.16b
  bit v6.16b, v16.16b, v17.16b
  bit v7.16b, v16.16b, v17.16b
  bit v8.16b, v16.16b, v17.16b
  bit v9.16b, v16.16b, v17.16b
  bit v10.16b, v16.16b, v17.16b
  bit v11.16b, v16.16b, v17.16b
  bit v12.16b, v16.16b, v17.16b
  bit v13.16b, v16.16b, v17.16b
  bit v14.16b, v16.16b, v17.16b
  bit v15.16b, v16.16b, v17.16b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40082	301	0	0	0	0	0	0	0	82	515	110	25	160100	100	160082	100	160000	500	5439651	0	40080	40039	40038	19973	0	3	20084	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	17	1	1	40035	0	160000	100	40100	40039	40039	40082	40039
160204	40038	300	0	0	0	0	0	0	0	40	61	110	25	160182	100	160082	100	160000	500	5439651	0	40019	40099	40038	20008	0	3	20057	160100	200	160000	200	480000	40099	40099	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40035	0	160000	100	40100	40100	40100	40039	40100
160204	40099	300	1	0	0	0	0	0	0	42	61	110	25	160182	100	160000	100	160000	500	5402633	0	40019	40099	40141	20022	0	3	19996	160100	200	160000	200	480000	40038	40057	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40096	0	160000	100	40039	40100	40100	40100	40039
160204	40038	300	1	0	0	0	0	0	0	0	40	0	25	160100	100	160082	100	160000	500	1280000	0	40080	40099	40099	19973	0	3	20057	160100	200	160000	200	480000	40099	40099	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40035	0	160000	100	40100	40100	40100	40039	40039
160204	40038	300	0	0	0	0	0	0	0	82	61	0	25	160100	100	160082	100	160000	500	5402633	0	40080	40099	40099	20008	0	3	20057	160100	200	160000	200	480000	40099	40099	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40096	0	160000	100	40039	40039	40039	40039	40040
160204	40038	300	1	0	0	0	0	9	0	82	726	0	25	160182	100	160000	100	160000	500	5402633	0	40080	40099	40038	20008	0	3	19995	160100	200	160000	200	480000	40099	40099	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	3	40124	25	160000	100	40039	40039	40039	40100	40058
160204	40038	300	0	0	0	0	0	0	0	82	61	110	25	160100	100	160082	100	160000	500	5402633	0	40019	40038	40099	19973	0	3	20057	160100	200	160000	200	480000	40099	40089	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40035	0	160000	100	40100	40100	40100	40100	40100
160204	40099	300	0	0	0	0	0	0	0	0	40	0	25	160100	100	160000	100	160000	500	1280000	0	40019	40038	40099	19973	0	3	19996	160100	200	160000	200	480000	40099	40099	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40096	0	160000	100	40100	40100	40100	40100	40039
160204	40038	300	1	0	0	0	0	0	0	82	40	110	25	160100	100	160082	100	160000	500	1280000	0	40080	40099	40099	19973	0	3	19996	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40096	0	160000	100	40100	40039	40039	40100	40100
160204	40099	300	0	0	0	0	0	0	0	82	61	110	25	160182	100	160082	100	160000	500	1280000	0	40080	40099	40038	19973	0	3	19996	160100	200	160000	200	480000	40038	40099	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	1	16	1	1	40035	0	160000	100	40100	40100	40100	40100	40128

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40146	299	0	0	0	0	0	0	0	0	0	66	0	25	160010	10	160023	10	160000	50	3997424	1	1	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	0	34	16	2	1	1	27	29	40140	0	20	8	0	160000	10	40039	40039	40058	40039	40039
160024	40038	299	0	0	0	0	0	0	0	0	0	63	0	25	160033	10	160000	10	160000	50	1280000	1	1	0	40019	40038	40057	19996	0	3	20037	160010	20	160000	20	480000	40057	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	0	18	16	2	1	1	29	18	40042	0	20	8	0	160000	10	40039	40058	40039	40039	40039
160024	40038	299	0	0	0	0	0	0	0	0	0	166	0	25	160010	10	160000	10	160000	50	1280000	1	1	0	40020	40039	40038	19996	0	3	20018	160010	20	160000	20	480000	40039	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	0	18	16	2	1	1	29	23	40044	0	20	8	0	160000	10	40039	40058	40039	40039	40039
160024	40038	300	0	0	0	0	0	0	0	42	0	67	0	25	160010	10	160001	10	160000	50	4728951	1	1	0	40019	40038	40057	19996	0	3	20037	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	2	0	17	16	2	1	1	29	17	40044	0	20	8	0	160000	10	40113	40039	40039	40039	40039
160024	40112	300	0	0	0	0	0	0	0	112	1	88	0	25	160010	10	160106	10	160000	50	1280000	1	1	0	40019	40062	40038	19996	0	3	20037	160010	20	160000	20	480000	40057	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	0	27	16	2	1	1	16	27	40044	0	20	7	0	160000	10	40039	40039	40039	40039	40113
160024	40038	299	0	0	0	0	0	0	0	0	0	63	0	25	160010	10	160023	10	160000	50	1280000	1	1	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40057	1	1	160021	10	9	10	10	160000	10	0	3	0	10022	3	2	1	0	29	16	2	1	1	29	29	40056	0	20	7	0	160000	10	40039	40113	40075	40113	40058
160024	40038	300	0	0	0	0	0	0	0	0	0	45	0	25	160116	10	160000	10	160000	50	1280000	1	1	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40057	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	0	29	16	2	1	1	29	29	40056	0	42	8	0	160000	10	40039	40089	40075	40039	40058
160024	40039	300	0	0	0	0	0	0	0	1	1	46	0	25	160010	10	160001	10	160000	50	1280000	1	1	0	40038	40038	40039	19996	0	3	20019	160010	20	160000	20	480000	40038	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	0	29	16	2	1	1	15	29	40063	0	20	8	0	160000	10	40058	40039	40058	40113	40039
160024	40038	300	0	0	0	0	0	0	0	0	0	67	149	25	160010	10	160001	10	160000	50	1280000	1	1	0	40056	40057	40057	19996	0	3	20037	160010	20	160000	20	480000	40057	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	0	27	16	2	1	1	29	29	40056	0	20	8	0	160000	10	40058	40039	40058	40040	40039
160024	40057	300	0	0	0	0	0	0	0	181	0	45	0	25	160010	10	160000	10	160000	50	1320000	1	1	0	40020	40038	40038	19996	0	3	20092	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	10022	3	1	1	0	24	16	2	1	1	28	17	40061	0	20	8	0	160000	10	40058	40113	40058	40039	40039

BIT (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations