Firestorm: BIT (vector, 8B) measurements

Code:

  bit v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	82	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	3	94	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	32	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	103	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	9	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bit v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	33	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	15	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	0	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	4	16	4	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	21	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	8	16	7	8	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	0	572	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	8	16	8	7	19785	0	10000	10	20085	20038	20038	20038	20038
10024	20037	150	0	0	0	0	1	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	6	16	7	8	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	27	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	8	16	8	8	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	18	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	7	16	7	8	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	8	16	8	7	19785	0	10000	10	20038	20038	20085	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	7	16	7	8	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	1	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	640	8	16	8	7	19822	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	7	16	8	7	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	0	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	7	16	7	6	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  bit v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	251	19687	25	10100	100	10000	125	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	4	3	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	1	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18744	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	714	1	16	1	1	19846	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	232	19687	25	10125	100	10000	100	10000	626	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	2	9	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	1	0	0	61	19687	25	10100	125	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	20	63	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	63	19687	25	10100	125	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18744	10125	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	17	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10125	125	10000	125	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	3	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	5	159	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	2	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	17	4	3	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10125	125	10000	125	10000	626	2847680	1	20018	20037	20037	18422	0	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	1	9	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	27	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	251	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	6	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	6	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	3	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	1	3	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  bit v0.8b, v1.8b, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20073	150	0	0	0	0	0	0	0	631	19676	25	10100	100	10000	100	10000	500	2848963	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	24	0	3	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	12	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10498	200	30000	20037	20037	5	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	9	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20085
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	3	16	2	2	19785	0	10000	10	20038	20038	20086	20084	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	1	3	88	675	19676	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	8	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	0	0	4043	0	640	2	24	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	12	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	156	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	82	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	3	2	640	2	16	2	2	19803	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	1028	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bit v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  bit v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  bit v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  bit v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  bit v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  bit v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  bit v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  bit v7.8b, v8.8b, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20065	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	4	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	59	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	9	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	228	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	4805	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20153	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	38	25	80100	100	80000	100	80000	500	640000	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20074	150	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20063	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	8	1	1	10	266	2	1	2	6	9	20056	2	20	0	1	160000	10	20051	20051	20051	20051	20060
160024	20059	150	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20050	3	21	80012	20	80000	20	240000	20076	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	8	5	1	6	259	2	2	3	9	9	20047	2	20	0	1	160000	10	20051	20051	20051	20060	20051
160024	20050	150	0	0	0	50	27	80012	12	80000	12	80000	62	640000	1	1	5	20040	20059	20059	3	21	80012	20	80000	20	240000	20085	20068	1	1	160021	10	9	10	10	160000	10	0	0	0	10035	8	5	1	6	245	4	2	1	10	7	20056	2	40	0	2	160000	10	20060	20060	20060	20060	20060
160024	20050	150	0	0	2	50	27	80012	12	80000	12	80000	62	640000	1	1	5	20040	20050	20059	3	21	80012	20	80000	20	240000	20085	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	10064	11	5	2	9	237	4	2	2	9	9	20047	2	20	0	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	2	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	20059	20050	3	21	80012	20	80000	20	240000	20063	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	11	5	2	7	244	4	2	2	6	10	20065	2	40	0	2	160000	10	20060	20060	20051	20051	20060
160024	20059	150	0	0	0	50	29	80012	12	80000	12	80000	62	640000	1	1	5	20040	20059	20059	3	21	80012	20	80000	20	240000	20063	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	10032	8	4	1	6	267	2	2	3	10	9	20056	2	40	0	2	160000	10	20060	20060	20051	20060	20060
160024	20050	150	0	0	0	430	29	80012	12	80000	12	80000	62	640000	1	1	5	20031	20050	20059	3	21	80012	20	80000	20	240000	20085	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10035	11	5	1	9	216	2	2	1	9	7	20047	2	40	0	2	160000	10	20051	20051	20051	20051	20051
160024	20059	150	0	0	0	44	27	80012	12	80000	12	80000	62	640000	1	1	5	20040	20050	20050	3	21	80012	20	80000	20	240000	20086	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10035	11	5	2	9	237	4	2	2	9	7	20056	2	20	0	2	160000	10	20051	20060	20060	20060	20051
160024	20059	150	0	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	20059	20059	3	21	80012	20	80000	20	240000	20085	20068	1	1	160021	10	9	10	10	160000	10	0	0	0	10035	11	5	2	9	244	4	2	3	7	9	20056	2	40	0	2	160000	10	20060	20060	20060	20060	20060
160024	20059	150	0	0	0	50	29	80012	12	80000	12	80000	62	640000	0	1	5	20040	20059	20059	3	21	80012	20	80000	20	240000	20086	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	11	5	2	6	274	6	2	3	9	6	20056	2	40	0	2	160000	10	20060	20060	20060	20060	20060

Test 6: throughput

Count: 16

Code:

  bit v0.8b, v16.8b, v17.8b
  bit v1.8b, v16.8b, v17.8b
  bit v2.8b, v16.8b, v17.8b
  bit v3.8b, v16.8b, v17.8b
  bit v4.8b, v16.8b, v17.8b
  bit v5.8b, v16.8b, v17.8b
  bit v6.8b, v16.8b, v17.8b
  bit v7.8b, v16.8b, v17.8b
  bit v8.8b, v16.8b, v17.8b
  bit v9.8b, v16.8b, v17.8b
  bit v10.8b, v16.8b, v17.8b
  bit v11.8b, v16.8b, v17.8b
  bit v12.8b, v16.8b, v17.8b
  bit v13.8b, v16.8b, v17.8b
  bit v14.8b, v16.8b, v17.8b
  bit v15.8b, v16.8b, v17.8b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40124	300	0	0	0	0	293	40	0	25	160100	100	160000	100	160000	500	1320000	1	40019	40038	40057	19973	0	3	20015	160100	200	160000	200	480000	40038	40057	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	0	1	16	1	1	40109	0	160000	100	40039	40058	40039	40039	40039
160204	40038	300	0	0	0	0	0	61	113	25	160123	100	160000	100	160000	500	1280000	1	40038	40038	40038	20007	0	3	19996	160100	200	160000	200	480000	40057	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	2	16	1	1	40035	0	160000	100	40039	40039	40096	40096	40039
160204	40038	300	0	0	0	0	0	82	0	25	160100	100	160078	100	160000	500	1280000	0	40019	40038	40038	20003	0	3	19996	160100	200	160000	200	480000	40095	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	0	1	16	1	1	40035	0	160000	100	40096	40039	40039	40039	40096
160204	40038	300	0	0	3	0	0	40	0	25	160100	100	160000	100	160000	500	1280000	0	40019	40038	40038	20003	0	3	19996	160100	200	160000	200	480000	40038	40095	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	0	1	16	1	2	40092	0	160000	100	40039	40096	40039	40039	40039
160204	40038	300	0	0	0	0	0	275	111	25	160178	100	160000	100	160000	500	1280000	1	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	480000	40095	40095	1	1	160201	100	99	100	100	160000	100	0	1	0	10110	0	1	16	1	1	40119	21	160000	100	40039	40105	40039	40039	40039
160204	40038	300	1	0	0	0	0	40	0	25	160100	100	160000	100	160000	500	5519418	1	40076	40038	40095	20003	0	3	19996	160100	200	160000	200	480000	40099	40038	1	1	160201	100	99	100	100	160000	100	0	3	3	10110	0	1	16	1	1	40036	0	160000	100	40096	40039	40039	40039	40039
160204	40095	300	0	0	0	0	0	40	0	25	160100	100	160000	100	160000	500	1280000	0	40019	40039	40038	19973	0	3	19996	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	0	1	17	1	1	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	61	111	25	160117	100	160000	100	160000	500	5519418	0	40076	40038	40038	19973	0	3	19996	160100	200	160000	200	480000	40095	40095	1	1	160201	100	99	100	100	160000	100	0	3	0	10110	0	1	28	1	1	40035	0	160000	100	40096	40118	40138	40039	40096
160204	40038	300	0	0	0	0	0	61	0	25	160100	100	160000	100	160000	500	5519418	1	40081	40038	40038	19973	0	3	19996	160100	200	160000	200	480000	40095	40095	1	1	160201	100	99	100	100	160000	100	0	1	0	10110	0	1	16	1	1	40035	0	160000	100	40039	40039	40102	40096	40039
160204	40039	300	0	0	12	0	0	124	0	25	160178	100	160000	100	160000	500	1280000	0	40019	40038	40038	19973	0	3	19996	160100	200	160000	200	480000	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	2	1	16	1	1	40035	0	160000	100	40039	40039	40101	40039	40096

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	0	0	0	51	110	25	160010	10	160000	10	160000	50	1280000	1	0	0	40019	40185	40038	20031	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10024	3	35	1	18	16	2	1	1	16	16	40096	20	8	160000	10	40100	40039	40039	40039	40039
160024	40038	300	0	0	0	81	45	0	25	160010	10	160001	10	160000	50	1280000	1	0	0	40093	40038	40039	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	28	1	6	16	2	1	1	6	16	40035	20	8	160000	10	40100	40039	40039	40039	40039
160024	40038	299	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	1280000	1	0	5	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40185	40099	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	29	1	5	16	2	1	2	6	13	40035	20	8	160000	10	40039	40100	40039	40039	40039
160024	40101	299	0	0	0	0	710	0	25	160011	10	160082	10	160000	50	1280000	1	0	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	31	2	16	16	2	1	1	16	6	40096	20	9	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	5362848	1	1	5	40019	40099	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	31	2	17	16	2	1	1	16	6	40035	20	8	160000	10	40039	40039	40039	40100	40040
160024	40038	300	0	0	0	0	45	0	25	160092	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	0	3	20079	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	29	2	6	16	2	1	1	5	16	40182	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	67	0	25	160010	10	160000	10	160000	50	1280000	1	1	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40185	40099	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	33	1	16	16	2	1	1	16	5	40035	20	8	160000	10	40039	40100	40186	40100	40039
160024	40099	300	0	0	0	0	67	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	11	31	2	16	16	4	1	1	16	16	40035	20	8	160000	10	40039	40039	40039	40100	40039
160024	40038	299	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	5438264	1	1	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	10022	8	31	1	16	16	2	1	1	16	16	40036	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	710	0	25	160010	10	160000	10	160000	50	1280000	0	1	5	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40038	40099	1	1	160021	10	9	10	10	160000	10	0	0	10022	3	6	1	16	16	2	1	1	16	6	40096	20	8	160000	10	40039	40039	40100	40039	40039

BIT (vector, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations