Firestorm: BSL (vector, 16B) measurements

Code:

  bsl v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	145	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	720	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	3	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bsl v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	4	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	204	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	712	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	726	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	4	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	4	16	4	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	3	4	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	18	640	3	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10304	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	24	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	3	640	2	16	2	2	19824	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	104	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20083
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	1	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18448	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	251	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	3	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	12	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  bsl v0.16b, v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	741	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	103	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	4	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	1050	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	346	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	1	640	2	16	2	2	19998	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	0	0	105	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  bsl v0.16b, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	15	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	18	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	726	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	57	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	12	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	12	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20021	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	12	103	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	25	1	3	19825	10000	100	20038	20038	20135	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	42	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	150	487	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	15	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20085	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	30	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	12	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20054	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	3	3	19785	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bsl v0.16b, v8.16b, v9.16b
  movi v1.16b, 0
  bsl v1.16b, v8.16b, v9.16b
  movi v2.16b, 0
  bsl v2.16b, v8.16b, v9.16b
  movi v3.16b, 0
  bsl v3.16b, v8.16b, v9.16b
  movi v4.16b, 0
  bsl v4.16b, v8.16b, v9.16b
  movi v5.16b, 0
  bsl v5.16b, v8.16b, v9.16b
  movi v6.16b, 0
  bsl v6.16b, v8.16b, v9.16b
  movi v7.16b, 0
  bsl v7.16b, v8.16b, v9.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	0	0	0	9	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	6	608	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10114	0	4	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	27	122	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	0	0	0	21	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240405	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	18	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	15	38	25	80100	100	80000	100	80000	500	640000	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10112	0	2	16	0	2	2	20060	0	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20092	150	0	0	27	44	25	80012	12	80000	12	80000	62	640000	0	1	20291	0	20049	20049	3	21	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10035	6	2	2	13	20	2	1	1	5	11	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	15	44	25	80012	12	80000	12	80000	62	640000	1	1	20257	0	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10033	3	1	1	11	20	2	1	1	6	11	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	15	44	25	80012	12	80000	12	80000	62	640000	1	1	20239	0	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10033	3	1	1	11	20	2	1	1	11	6	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	49	25	80012	12	80000	12	80000	62	640000	1	1	20195	0	20045	20053	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10029	3	1	1	6	20	2	1	1	10	12	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20241	0	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10033	3	1	1	6	20	2	1	1	10	6	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	12	44	25	80012	12	80000	12	80000	62	640000	1	1	20197	0	20045	20045	3	21	80012	20	80000	20	240000	20049	20049	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10035	6	2	2	9	24	4	2	2	5	11	20046	2	30	160000	10	20050	20050	20050	20050	20050
160024	20049	150	0	0	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20227	0	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10033	3	1	1	12	20	2	1	1	6	11	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	18	44	25	80012	12	80000	12	80000	62	640000	0	1	20204	0	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10034	3	1	1	7	20	2	1	1	6	11	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	0	263	25	80012	12	80000	12	80000	62	640000	1	1	20207	0	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10034	3	1	1	10	20	2	1	1	11	11	20042	2	15	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	0	18	44	25	80012	12	80000	12	80000	62	640000	1	1	20218	0	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10034	3	1	1	11	20	2	1	1	11	6	20042	2	15	160000	10	20046	20046	20046	20046	20046

Test 6: throughput

Count: 16

Code:

  bsl v0.16b, v16.16b, v17.16b
  bsl v1.16b, v16.16b, v17.16b
  bsl v2.16b, v16.16b, v17.16b
  bsl v3.16b, v16.16b, v17.16b
  bsl v4.16b, v16.16b, v17.16b
  bsl v5.16b, v16.16b, v17.16b
  bsl v6.16b, v16.16b, v17.16b
  bsl v7.16b, v16.16b, v17.16b
  bsl v8.16b, v16.16b, v17.16b
  bsl v9.16b, v16.16b, v17.16b
  bsl v10.16b, v16.16b, v17.16b
  bsl v11.16b, v16.16b, v17.16b
  bsl v12.16b, v16.16b, v17.16b
  bsl v13.16b, v16.16b, v17.16b
  bsl v14.16b, v16.16b, v17.16b
  bsl v15.16b, v16.16b, v17.16b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40083	301	0	0	0	29	0	25	160140	100	160008	100	160023	500	1280132	1	40019	40085	40038	19998	6	19989	160120	200	160032	200	480096	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	2	16	0	0	40035	160000	100	40039	40039	40075	40039	40039
160204	40074	301	0	0	0	29	0	25	160108	100	160081	100	160021	500	1280132	1	40019	40099	40038	19977	6	20050	160120	200	160032	200	480096	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40082	160000	100	40039	40039	40039	40039	40075
160204	40038	300	0	0	0	55	0	25	160108	100	160040	100	160020	500	5438423	0	40019	40038	40099	19977	6	19989	160120	200	160032	200	480096	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10136	0	16	0	0	40071	160000	100	40039	40039	40075	40086	40039
160204	40038	300	0	0	0	435	34	25	160108	100	160058	100	160020	500	5438423	0	40019	40038	40099	19977	6	19989	160120	200	160032	200	480096	40038	40099	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40075	40039
160204	40038	300	0	0	0	29	0	25	160108	100	160008	100	160020	500	5362989	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	480096	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40096	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	29	0	25	160108	100	160008	100	160020	500	1280132	1	40080	40099	40038	19977	6	19989	160120	200	160032	200	480096	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	29	0	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	20012	6	19989	160121	200	160032	200	480096	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40096	160000	100	40100	40039	40039	40039	40100
160204	40099	300	0	0	0	29	0	25	160108	100	160009	100	160021	500	1280132	0	40019	40038	40038	19977	6	19989	160120	200	160032	200	480096	40038	40085	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40075	40039
160204	40038	300	0	0	0	29	0	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	480096	40099	40077	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40039	40039	40039	40100
160204	40038	300	0	0	0	29	0	25	160108	100	160008	100	160020	500	1280132	1	40020	40038	40038	19977	6	20036	160120	200	160032	200	480096	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40035	160000	100	40039	40075	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40135	300	1	0	0	0	0	0	0	32	0	45	0	25	160052	10	160000	10	160000	50	1280000	1	1	10	40056	40038	40067	20015	0	3	20018	160010	20	160000	20	480000	40038	40067	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10024	13	2	1	8	16	2	1	2	5	5	40035	0	40	8	160000	10	40039	40113	40057	40040	40082
160024	40038	300	0	0	0	0	0	0	0	0	0	67	3	25	160010	10	160001	10	160000	50	1280000	4	1	10	40020	40081	40056	19996	0	3	20018	160010	20	160000	20	480000	40038	40082	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	13	6	2	4	16	4	1	2	4	4	40035	0	20	16	160000	10	40039	40039	40039	40113	40039
160024	40038	300	0	0	0	0	0	0	0	0	0	67	0	25	160060	10	160000	10	160000	50	1280000	0	1	10	40019	40038	40112	20037	13	3	20019	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10072	13	6	1	5	16	2	1	1	4	3	40109	0	20	8	160000	10	40039	40064	40113	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	0	67	149	25	160116	10	160067	10	160000	50	1280000	1	1	10	40093	40112	40038	19996	0	3	20092	160010	20	160000	20	480000	40038	40112	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10024	16	5	2	4	16	2	2	1	6	6	40078	0	40	8	160000	10	40039	40039	40082	40039	40058
160024	40081	299	0	0	0	0	0	0	0	0	0	51	0	25	160010	10	160000	10	160000	50	4728951	5	1	10	40019	40039	40112	20006	0	3	20036	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10024	13	5	2	6	16	4	1	2	4	3	40109	0	20	8	160000	10	40039	40039	40039	40076	40039
160024	40038	300	0	0	0	0	0	0	0	0	0	732	0	25	160010	10	160000	10	160000	50	1280000	3	1	10	40019	40038	40067	19996	0	3	20061	160010	20	160000	20	480000	40063	40063	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	13	5	2	4	16	2	1	2	6	6	40084	0	20	16	160000	10	40082	40039	40039	40082	40082
160024	40038	300	0	0	0	0	0	0	0	0	0	259	390	224	161645	10	161247	10	161339	55	3136446	4	1	10	40681	40738	40915	20426	42	59	20202	161249	20	161715	20	484728	40726	40820	11	1	160021	10	9	10	10	160000	10	2	4	3	0	2	4600	4	0	0	10222	13	5	1	5	117	2	1	1	10	14	40401	1	20	10	160000	10	40866	40716	40788	40895	41043
160024	41450	304	0	0	1	10	10	1332	792	346	0	1943	346	242	161624	11	161605	12	161795	65	3057870	1	1	10	40751	40785	40531	20406	10	48	20609	161451	20	161709	20	485214	40777	40716	11	1	160021	10	9	10	10	160000	10	4	0	3	1	2	5548	4	0	0	10243	13	5	1	4	128	2	1	1	4	9	40620	2	20	7	160000	10	41053	41122	41073	40936	41034
160024	41139	306	0	1	0	13	12	1716	1144	370	0	2488	1017	285	161891	14	162022	10	160915	66	3385754	4	1	10	40906	41410	40949	20346	125	65	20853	161137	20	161508	20	485025	41178	41267	14	1	160021	10	9	10	10	160000	10	0	0	0	0	0	5993	4	0	0	10167	16	6	2	4	16	2	1	1	4	4	40109	0	20	8	160000	10	40039	40115	40056	40039	40039
160024	40038	300	0	0	0	0	0	0	0	0	0	63	0	25	160010	10	160042	10	160000	50	1280000	5	1	10	40019	40038	40112	19996	0	3	20018	160010	20	160000	20	480000	40038	40087	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	0	10022	13	5	1	5	16	2	1	8	5	5	40035	0	20	8	160000	10	40039	40076	40039	40113	40113

BSL (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations