Firestorm: BSL (vector, 8B) measurements

Code:

  bsl v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	2	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2084	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  bsl v0.8b, v1.8b, v2.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	19687	20021	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18424	13	18795	10255	200	10000	200	30000	20134	20178	1	1	10201	100	99	100	100	10000	100	0	0	710	1	4	16	2	3	19825	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	94	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	2	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	6	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	3	0	710	1	2	16	3	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	15	186	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	15	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	3	0	710	1	2	16	2	3	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1	61	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	0	25	10100	100	10000	100	10000	500	2847680	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	4	9	710	1	2	16	2	2	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	168	19676	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	6	16	2	3	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	4	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	21	149	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	640	3	16	2	2	19785	10000	10	20132	20038	20038	20038	20038
10024	20037	150	1	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	156	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10608	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	4	5	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	6	3	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	5	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  bsl v0.8b, v0.8b, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18429	6	18741	10100	200	10008	200	30024	20037	20037	1	1	10201	100	99	100	100	10000	100	4	69	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10012	100	10000	500	2847680	1	20018	20037	20037	18429	7	18740	10100	200	10008	200	30024	20037	20037	1	1	10201	100	99	100	100	10000	100	8	12	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	536	19687	25	10100	100	10000	100	10000	626	2847680	1	20018	20037	20037	18429	6	18740	10100	200	10008	200	30024	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	739	0	16	0	0	19802	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18429	7	18740	10100	200	10008	200	30024	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18429	7	18740	10100	200	10008	200	30024	20037	20037	1	1	10201	100	99	100	100	10000	100	0	6	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	82	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	19785	10000	10	20084	20038	20085	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	8	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10022	10	9	10	10	10000	10	0	0	3	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  bsl v0.8b, v1.8b, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	536	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	2	33	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	12	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	3	710	2	16	2	2	19791	0	10000	100	20085	20038	20038	20038	20182
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	131	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	2	3	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20085	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	2	34	2	2	19791	3	10000	100	20038	20087	20038	20038	20038
10204	20037	150	1	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	103	19687	25	10100	100	10048	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	2	0	710	2	16	2	2	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	155	0	0	0	0	0	715	19687	25	10010	10	10000	13	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	3	640	2	16	3	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19676	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	9	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	20018	20037	20037	18444	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  bsl v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  bsl v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  bsl v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  bsl v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  bsl v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  bsl v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  bsl v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  bsl v7.8b, v8.8b, v9.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	38	25	80100	100	80000	100	80000	500	640000	0	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	31	0	108	10111	5	1	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	506	640792	1	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	2	0	0	10111	0	1	1	72	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10142	5	0	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160205	20063	151	0	38	25	80100	100	80000	100	80000	500	640000	0	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	0	0	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	608	25	80100	100	80000	100	80000	500	640000	1	5	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	5	0	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	5	1	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	0	0	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	0	0	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	151	0	38	25	80100	100	80000	100	80000	500	640000	0	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	0	0	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064
160204	20063	150	0	38	25	80100	100	80000	100	80000	500	640000	0	0	20044	20063	20063	3	21	80100	200	80000	200	240000	20063	20063	1	1	160201	100	99	100	100	160000	100	0	0	0	10111	0	0	1	16	1	1	20060	160000	100	20064	20064	20064	20064	20064

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20079	150	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10032	3	1	1	9	20	2	1	1	9	10	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10032	3	1	1	11	20	2	1	2	9	9	20042	2	30	0	160000	10	20052	20046	20046	20046	20046
160024	20045	150	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10035	3	1	1	9	20	2	1	1	11	11	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10033	3	1	1	12	20	2	1	1	9	10	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	6	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	3	1	1	9	20	2	1	1	11	12	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20113	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	3	1	1	8	20	2	1	1	11	9	20042	2	15	0	160000	10	20046	20046	20046	20046	20046
160024	20045	150	0	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	3	0	10032	3	1	1	10	20	2	1	1	12	9	20042	2	15	0	160000	10	20046	20046	20050	20050	20050
160024	20045	150	12	44	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20122	2	1	160021	10	9	10	10	160000	10	2	1	0	0	10035	3	1	1	11	20	2	1	1	11	12	20042	2	15	0	160000	10	20046	20046	20046	20046	20050
160024	20045	150	12	50	25	80012	12	80000	12	80000	62	640000	1	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	1	3	0	10033	3	1	1	12	20	2	1	1	9	9	20042	2	15	0	160000	10	20052	20050	20050	20050	20046
160024	20049	150	0	44	25	80012	12	80000	12	80000	62	640000	0	1	20026	20045	20045	3	21	80012	20	80000	20	240000	20045	20045	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10034	3	1	1	10	20	2	1	1	10	9	20042	2	15	0	160000	10	20046	20050	20046	20046	20046

Test 6: throughput

Count: 16

Code:

  bsl v0.8b, v16.8b, v17.8b
  bsl v1.8b, v16.8b, v17.8b
  bsl v2.8b, v16.8b, v17.8b
  bsl v3.8b, v16.8b, v17.8b
  bsl v4.8b, v16.8b, v17.8b
  bsl v5.8b, v16.8b, v17.8b
  bsl v6.8b, v16.8b, v17.8b
  bsl v7.8b, v16.8b, v17.8b
  bsl v8.8b, v16.8b, v17.8b
  bsl v9.8b, v16.8b, v17.8b
  bsl v10.8b, v16.8b, v17.8b
  bsl v11.8b, v16.8b, v17.8b
  bsl v12.8b, v16.8b, v17.8b
  bsl v13.8b, v16.8b, v17.8b
  bsl v14.8b, v16.8b, v17.8b
  bsl v15.8b, v16.8b, v17.8b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40060	300	0	0	0	0	0	0	0	1354	0	25	160100	100	160000	100	160000	500	4728951	1	40019	40038	40126	20035	0	3	20075	160100	200	160000	200	480000	40038	40117	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	40109	0	160000	100	40039	40127	40039	40189	40127
160204	40038	301	0	0	0	0	0	0	106	1272	149	25	160100	100	160000	100	160000	500	5486390	1	40169	40038	40126	20035	0	3	20146	160100	200	160000	200	480000	40126	40188	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	40062	0	160000	100	40127	40189	40127	40189	40039
160204	40126	300	0	0	0	0	0	0	125	1408	149	25	160131	100	160000	100	160000	500	1280000	0	40019	40038	40065	19973	0	3	19996	160100	200	160000	200	480000	40038	40112	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	2	16	1	1	40035	0	160000	100	40127	40039	40127	40039	40039
160204	40112	300	0	0	0	0	0	0	125	792	205	25	160225	100	160209	100	160000	500	5486390	0	40019	40038	40126	20035	0	3	20084	160100	200	160000	200	480000	40126	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	40035	0	160000	100	40127	40113	40127	40039	40039
160204	40038	301	0	0	0	0	0	0	0	1235	0	25	160225	100	160125	100	160000	500	1280000	1	40107	40126	40188	20093	0	3	19996	160100	200	160000	200	480000	40038	40126	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	40123	0	160000	100	40039	40039	40127	40286	40039
160204	40038	300	0	0	0	0	0	0	0	1184	382	25	160188	100	160000	100	160000	500	5486390	0	40169	40038	40188	20035	0	3	19997	160100	200	160000	200	480000	40188	40126	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	40109	0	160000	100	40039	40127	40189	40127	40189
160204	40126	300	0	0	0	0	0	0	111	124	149	25	160100	100	160000	100	160000	500	1280000	0	40019	40038	40112	19973	0	3	20023	160100	200	160000	200	480000	40038	40126	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	1	1	40062	0	160000	100	40127	40039	40127	40189	40127
160204	40188	300	0	0	0	0	0	0	0	1233	0	25	160100	100	160000	100	160000	500	5486390	0	40019	40038	40126	20035	0	3	20084	160100	200	160000	200	480000	40126	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	3	16	3	1	40035	0	160000	100	40039	40039	40039	40127	40039
160204	40038	300	0	0	0	0	0	0	0	1280	205	25	160100	100	160000	100	160000	500	1280000	0	40019	40038	40126	20035	3	3	20084	160100	200	160000	200	480000	40038	40106	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	3	16	1	1	40123	0	160000	100	40127	40039	40127	40039	40209
160204	40118	299	0	0	0	0	0	0	0	1298	0	25	160100	100	160000	100	160000	500	4728951	1	40093	40063	40038	20014	13	3	20070	160100	200	160000	200	480000	40112	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	0	16	1	1	40035	0	160000	100	40127	40039	40127	40189	40127

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40103	300	0	2	0	23	615	0	25	160150	10	160000	10	160000	50	1280000	1	1	5	40020	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40057	40119	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	8	2	1	13	16	3	2	1	10	9	40172	30	5	160000	10	40039	40039	40039	40090	40039
160024	40038	299	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	5534021	1	1	5	40038	40057	40038	20000	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	3	1	13	16	2	1	1	13	12	40090	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	45	0	25	160010	10	160112	10	160000	50	1280000	1	1	5	40019	40038	40144	19996	0	3	20018	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	4	1	12	16	2	1	1	9	12	40054	15	5	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	1537	0	25	160211	10	160000	10	160000	50	1280000	1	1	5	40019	40074	40183	19996	0	3	20018	160010	20	160000	20	480000	40217	40175	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	4	1	10	16	2	1	1	11	11	40035	15	5	160000	10	40039	40039	40039	40040	40039
160024	40038	300	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40047	40060	40038	20134	23	3	20019	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	5	1	9	16	2	1	1	12	9	40167	15	5	160000	10	40089	40039	40066	40066	40067
160024	40105	299	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40156	40175	40175	20057	0	3	20018	160010	20	160000	20	480000	40038	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	6	1	13	16	2	1	1	12	11	40054	15	5	160000	10	40039	40039	40094	40184	40145
160024	40057	300	0	0	0	0	67	336	25	160208	10	160000	10	160000	50	5560258	1	1	5	40019	40038	40038	19996	0	3	20037	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	6	1	13	16	2	1	1	11	11	40141	15	5	160000	10	40039	40040	40039	40058	40039
160024	40038	299	0	0	0	0	45	0	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	0	3	20099	160010	20	160000	20	480000	40038	40087	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	5	1	11	16	2	1	1	9	11	40035	15	5	160000	10	40039	40039	40039	40039	40176
160024	40038	300	0	0	0	198	45	0	25	160010	10	160069	10	160000	50	1280000	1	1	5	40020	40038	40038	19996	0	3	20018	160010	20	160000	20	480000	40055	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	5	1	12	16	2	1	1	10	10	40035	15	6	160000	10	40145	40086	40039	40176	40039
160024	40038	300	0	0	0	69	45	0	25	160270	10	160001	10	160000	50	1319997	1	1	5	40075	40038	40217	19996	0	3	20019	160010	20	160000	20	480000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10022	8	5	1	10	16	2	1	1	9	8	40172	15	5	160000	10	40039	40039	40039	40039	40086

BSL (vector, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations