Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CLZ (vector, 16B)

Test 1: uops

Code:

  clz v0.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371600611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420851500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645211201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038
100420371500611686251000100010002645210201820372037157131895100010001000203720371110011000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  clz v0.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371501006119686251012512510000125100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000710217221979125100001002003820038200382003820038
10204200371500006119686251010010010000100100006262847521020018200372003718421318745102542001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000012019686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100030071011611197910100001002003820038200382003820038
1020420037150000611968625101001001000010010000500284752102001820037200371842131874510125200100002001000020037200371110201100991001001000010002442071011611197910100001002003820038200382003820038
1020420037150000125619686251012512510000125100006262847521020018200372003718442318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718429318745101002001000020010000200372003711102011009910010010000100010071011611197910100001002003820038200382003820038
1020420037150000749196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000230071021611197910100001002003820038200382003820038
10204200371500006119686251010012510000125100006262847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718421318744101252001000020010000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000002981968625100101010000101000050284752112001820084201321844331876710010201000020100002003720037111002110910101000010010640316331978610000102003820038200382003820038
100242003715000001031968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500000821968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500300611968625100101010000101000050285131312001820037200371844331876710010201000020100002003720037111002110910101000010010640316331978610000102003820038200382003820038
10024200371500016203181968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
100242003715000001031968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
100242003715000001511968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
1002420037150000027519686251001010100001010000502847521020018200372003718443111876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  clz v0.16b, v8.16b
  clz v1.16b, v8.16b
  clz v2.16b, v8.16b
  clz v3.16b, v8.16b
  clz v4.16b, v8.16b
  clz v5.16b, v8.16b
  clz v6.16b, v8.16b
  clz v7.16b, v8.16b
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500050258010810080008100800205006401320200192003820038997776998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039
80204200381500094258010810080008100800205006401321200192003820038997706998980120200800322008003220038200381180201100991001008000010002911151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401321200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039
802042003815003115258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401321200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039
802042003815002429258010810080008100800205006401321200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401320200192003820038997706998980120200800322008003220038200381180201100991001008000010000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)0e191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150020008725800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000502000316342003580000102003920039200392003920039
8002420038149000004525800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000502000316442003580000102003920039200392003920039
8002420038150000003925800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000502000516542003580000102003920039200392003920039
80024200381500009606225800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000502000316442003580000102003920039200392003920039
8002420038150000003925800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000502000316342003580000102003920039200392003920039
8002420038150000003925800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010003502000316442003580000102003920039200392003920039
8002420038150000003925800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010100502000516552003580000102003920039200392003920039
80024200381500000014625800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000502000416442003580000102003920039200392003920039
8002420038150001003925800101080000108000050640000010200192003820038999631001880010208000020800002003820038118002110910108000010000502000416442003580000102003920039200392003920039
8002420038150000003925800101080000108000050640000000200192003820038999631001880010208000020800002003820038118002110910108000010000502000516452003580000102003920039200392003920039