Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CLZ (vector, 4S)

Test 1: uops

Code:

  clz v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715306116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716306116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037153006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  clz v0.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000611968625101001001000010010000500284878520018200372003718421318745101002001000020010000200372003711102011009910010010000100001371011611197910100001002003820038200382003820038
102042003715000004221968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100002071011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100003371011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100002371011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000371011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752120018200372003718421318745101002001000020010165200372003711102011009910010010000100000371011611197910100001002003820038200382003820038
10204200851500000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100001671011611197910100001002003820038200382003820038
102042003715000006119686251010010010000100100005002847521200182003720037184213187451010020010000200100002003720037111020110099100100100001000016371011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752120018200372003718421318745101002001000020010000200372003711102011009910010010000100000371011611197910100001002003820038200382003820038
10204200371500000611968625101001001000010010000500284752120018200372003718421318745101002001000020010167200372003711102011009910010010000100002071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500120611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010200640416441978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000102900640316341978610000102003820038200382003820038
100242003715001201061968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010100640316441978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010100640316341978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752102001820037200371844331876710010201018020100002003720037111002110910101000010000640416441978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316431978610000102003820038200382003820038
1002420037150000611968625100221210000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010030640316431978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316431978610000102003820038200382003820038
1002420037150000611968625100101010000101000050284752112001820037200371844331876710163201000020100002003720037111002110910101000010030640416441978610000102003820038200382003820038
10024200841500001031968643100101010012101000050284752112001820037200371844331876710010201000020100002003720084111002110910101000010460640416441978610000102003820038200382003820085

Test 3: throughput

Count: 8

Code:

  clz v0.4s, v8.4s
  clz v1.4s, v8.4s
  clz v2.4s, v8.4s
  clz v3.4s, v8.4s
  clz v4.4s, v8.4s
  clz v5.4s, v8.4s
  clz v6.4s, v8.4s
  clz v7.4s, v8.4s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006815000292580108100800081008002050064013220019200382003899776998980120200800322008013120038200381180201100991001008000010007811151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000311151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180410020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000311151180160020035800001002003920039200392003920039
802042003815001229258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000311151180160020035800001002003920039200392003920039
802042003815000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010030011151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001001311151180160020035800001002003920039200392003920039
80204200381520029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001001611151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000311151180160020035800001002003920039200392003920039
80204200381500029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151180160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfl1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150000002000038272580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050210114161017200350080000102003920050200392003920039
80024200381501000000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050210117161717200350080000102003920066200392003920039
80024200381501000000000704258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000905021011716916200350080000102003920050200392003920039
8002420038149100000000039258001010803751080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000020305021018161717200350080000102003920050200392003920039
80024200381491000000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000050210114161714200350080000102003920050200392003920039
8002420038150100000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000005021011716178200350080000102003920050200392003920039
80024200381501000000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050210117161017200350080000102003920050200392003920039
80024200381501000000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000100050210117161017200350080000102003920050200392003920039
8002420038150100000000060258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000010305021019161714200830080000102003920050200392003920039
80024200381501000000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000050210117161717200350080000102003920066200392003920039