Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (register, 16B)

Test 1: uops

Code:

  cmeq v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160611687251000100010002646801201820372037157231895100010002000203720371110011000000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000005773216221787100020382038203820382038
10042037153611687251000100010002646801201820372037157231895100010002000203720371110011000220673216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000000073216221787100020382038203820382038
10042037160611687251000100010002646801201820372037157231895100010002000203720371110011000000073216221787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000001273216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150486119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371502646119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150216119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150126119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371490104019687251010010010000100100005002847680200180200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680200180200372003718422318745102582001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001013640216221978510000102003820038200382003820038
1002420037150044119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010072640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001050640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100221091010100001039640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001020640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmeq v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150096119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820133
1020420037149006119687251010010010000100101525002847680200542003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200862003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001001007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001001007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820231
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010021037101161119791100001002003820085200382003820038
10204200371500010319687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000020337341161119791100001002003820038200382003820038
1020420037150098219687251010010010000100100005002847680200182003720037184267187451010020010000200200002003720037111020110099100100100001001020237101161119791100001002003820038200382003820038
1020420037150006119687251010010010012100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001001037321161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150001561968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001020640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
1002420037150027611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012006502003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmeq v0.16b, v8.16b, v9.16b
  cmeq v1.16b, v8.16b, v9.16b
  cmeq v2.16b, v8.16b, v9.16b
  cmeq v3.16b, v8.16b, v9.16b
  cmeq v4.16b, v8.16b, v9.16b
  cmeq v5.16b, v8.16b, v9.16b
  cmeq v6.16b, v8.16b, v9.16b
  cmeq v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100029511021611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100030511011611200350800001002003920039200392003920039
8020520048150000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100010511011611200350800001002003920039200392003920088
8020420038150000402580100100800001008000056564000012001920038200389973399968010020080000200160000200382003811802011009910010080000100016511011611200350800001002003920039200392003920039
802042003815000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000198511011611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100030511011611200350800001002003920039200392003920039
8020420038150000103258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000198511011611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000511011611200350800001002003920039200392003920039
8020420038150000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100003511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100000000502003162320035080000102003920039200392003920039
80024200381500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100000000502002162320035080000102003920039200392003920039
80024200381500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100002000502016166620035080000102003920039200392003920039
80024200381500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100000000502003163220035080000102003920039200392003920039
80024200381500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100000000502003163320035080000102003920039200392003920039
80024200381500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100000000502005163320035080000102003920039200392003920039
80024200381500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100000000502005163620035080000102003920039200392003920039
80024200381500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100001000502002166520035080000102003920039200392003920039
80024200381500000000039258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100001000502003162320035080000102003920039200392003920039
80024200381500100000081258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100000000502003162320035080000102003920039200392003920090