Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (register, 2D)

Test 1: uops

Code:

  cmeq v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371503082168725100010001000264680020182037203715723189510001000200020372037111001100073216111787100020382038203820382038
10042037160061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
100420371600112168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037160661168725100010001000264680120182037203715723189510001000200020372037111001100073116111787100020382038203820382038
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq v0.2d, v0.2d, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000124196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000087196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000187196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000207101161119791100001002003820038200382003820038
102042003715010061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000161196762510100100100001001000050028476800201262003720084184228187631028020010000200200002003720037111020110099100100100001000202023007101251119791100001002003820038200382003820038
1020420037150000103196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000009006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000003006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
10024200371500000240053619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820085
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150000027006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150000039006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmeq v0.2d, v1.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150396119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371503246119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119676251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150053619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715096119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150126119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715036119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371501986119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150069611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500204611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715001801071968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150021611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150018611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmeq v0.2d, v8.2d, v9.2d
  cmeq v1.2d, v8.2d, v9.2d
  cmeq v2.2d, v8.2d, v9.2d
  cmeq v3.2d, v8.2d, v9.2d
  cmeq v4.2d, v8.2d, v9.2d
  cmeq v5.2d, v8.2d, v9.2d
  cmeq v6.2d, v8.2d, v9.2d
  cmeq v7.2d, v8.2d, v9.2d
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015000360402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051103162220035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
802042003815000005152580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
8020420038150003120402580100100800001008000050064000002008220038200389973399968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381500014488402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
8020420038150000023025801001008000010080000500640000120019200382003899732599968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
8020420038150002310402580100100800001008000050064000012001920038200389982399968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039
80204200381500000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001516111120035080000102003920039200392003920039
800242003815000039258001010800001080000506400002001920038200389996310018800102080000201600002003820038118002110910108000010050200131610920035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001216121320035080000102003920039200392003920039
8002420038150010392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001316121220035080000102003920039200392003920039
80024200381500015392580107108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001016131120035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001016121020035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001016141420035080000102003920039200392003920039
8002420038150000392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001316121120035080000102003920039200392003920039
80024200381500005142580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001216131220035080000102003920039200392003920039
8002420038150010392580010108000010800005064000020019200382003899963100188001020800002016000020038200381180021109101080000100502001216101120035080000102003920039200392003920039