Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (register, 2S)

Test 1: uops

Code:

  cmeq v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371600611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203715088611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
1004203716001051687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073124111787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371500611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500001206119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000006119676251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000000438719687251010010010000100100005002847680020018200372003718422318745101002041000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100101525002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102008620038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmeq v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768000200180200372003718422318745101002001000020020000200372003711102011009910010010000100007100011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680002001802003720037184223187451010020010000200200002003720037111020110099100100100001000071000116111979125100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768010200180200372003718422318745101002001000020020000200372003711102011009910010010000100007100011612197910100001002003820038200862003820038
1020520037150000611968725101001001000010010000500284768000200180200372003718422318744101002001000020020000200372003711102011009910010010000100007100011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768010200180200372003718422318745101002001000020020000200372003711102011009910010010000100007100011611197910100001002003820038200382003820038
1020420037150002071031968725101001001000010010000500284768000200180200372003718422318745101002001000020020000200372003711102011009910010010000100007100011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768000200180200372003718422318745101252001000020020000200372003711102011009910010010000100007100011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768000200180200372003718422318745101002001000020020000200372003711102011009910010010000100007100011611197910100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768000200180200372003718422318745101002001000020020000200372003711102011009910010010000100007100011611197910100001002003820038200382003820038
10204200371500039611968725101001001000010010000500284768000200180200372003718422318745101002001000020020000200372003711102011009910010010000100017100011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000100061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000002706402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000095196672510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196672510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402163219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmeq v0.2s, v8.2s, v9.2s
  cmeq v1.2s, v8.2s, v9.2s
  cmeq v2.2s, v8.2s, v9.2s
  cmeq v3.2s, v8.2s, v9.2s
  cmeq v4.2s, v8.2s, v9.2s
  cmeq v5.2s, v8.2s, v9.2s
  cmeq v6.2s, v8.2s, v9.2s
  cmeq v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051104162220035800001002003920039200392003920039
802042003815000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051102162220035800001002003920039200392003920039
802042003815000082258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000651102162220035800001002003920039200392003920039
802042003815000940258010010080000100800005006400000200192007520038997339996801002008000020016000020038200381180201100991001008000010000051102162220035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100001551102162220035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100001551102162220035800001002003920039200392003920039
80204200381500015402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100006351102162220035800001002003920039200392003920039
802042003815000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051102162220035800001002003920039200392003920039
802042003815000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051102162220035800001002003920039200392003920039
802042003815000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000951102162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000039258001010800001080000506400002001902003820038999631001880010208000020160000200382003811800211091010800001005020716342003580000102003920039200392003920039
800242003815000039258001010800001080000506400002001902003820038999631001880010208000020160000200382003811800211091010800001095020416432003580000102003920039200392003920039
800242003815000039258001010800001080000506400002001902003820038999631001880010208000020160000200382003811800211091010800001005020416432003580000102003920039200392003920039
800242003815013039258001010800001080000506400002001902003820038999631001880010208000020160000200382003811800211091010800001005020416432003580000102003920039200392003920039
80024200381490003925800101080000108000050640000200190200382003899963100188001020800002016000020038200381180021109101080000101505020416542003580000102003920039200392003920039
800242003815000039258001010800001080000506400002001902003820038999631001880010208000020160000200382003811800211091010800001005020416432003580000102003920039200392003920039
800242003815000039258001010800001080000506400002001902003820038999631001880010208000020160000200382003811800211091010800001035020316342003580000102003920039200392003920039
8002420038150002739258001010800001080000506400002001902003820038999631001880010208000020160000200382003811800211091010800001005020416472003580000102003920039200392003920039
800242003815000039258001010800001080000506400002001902003820038999631001880010208000020160000200382003811800211091010800001005020516462003580000102003920039200392003920039
8002420038150000392580010108000010800005064000020019020038200389996310018800102080000201600002003820038118002110910108000010965020416432003580000102003920039200392003920039