Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (register, 4H)

Test 1: uops

Code:

  cmeq v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000373216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468012018203720371572318951000100020002037203711100110000373216221787100020382038203820382038
1004203715040516872510001000100026468012018203720371572318951000100020002037203711100110001073216221787100020382038203820382038
100420371512391168725100010001000264680120182037203715723189510001000200020372037111001100001273216221787100020382038203820382038
1004203715216116872510001000100026468012018203720371572318951000100020002037203711100110000373216221787100020382038203820382038
100420371508216872510001000100026468012018208320371572318951000100020002085203711100110000073216221787100020382074203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200612003718422318745101002001000020020000200372003711102011009910010010000100430710116111979114100001002003820038200382003820038
102042003715000542196764410116117100121001000050028476802001820037200371842631874510100200100002002000020037200371110201100991001001000010000271011611197912100001002008520086200862008620038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010033071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010006071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010010071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010020640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010010640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmeq v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968725101001001000010010000500284768002001820037200371842971874010100200100082002001620037200371110201100991001001000010000001117180160019801100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842961874010100200100082002001620037200371110201100991001001000010000001117170160019801100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842961874010100200100082002001620037200371110201100991001001000010000001117170161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000001710007101161119791100001002003820086200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371843931874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss data (0b)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9aaacc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371501000008219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000006403162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100220300200046402163119785210000102013220038201342008520227
1002420037150002132880153419687441003610100001110152772847680020162200372008518444318767100102010000202000020084200842110021109101010000102400041596127283242219785010000102003820038200382003820038
10024200371500020006119687251001010100001010000722847680020090200372003718444318767100102010000202000020037200371110021109101010000100001000006402162219785010000102008620085200382003820084
10024200371500000006119687251001010100001010000602847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
1002420037150000017606119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000100006402322219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318786100102010000202000020037200371110021109101010000100020000026402162219785010000102003820038200382003820038
10024200371500006006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000306402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100002000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmeq v0.4h, v8.4h, v9.4h
  cmeq v1.4h, v8.4h, v9.4h
  cmeq v2.4h, v8.4h, v9.4h
  cmeq v3.4h, v8.4h, v9.4h
  cmeq v4.4h, v8.4h, v9.4h
  cmeq v5.4h, v8.4h, v9.4h
  cmeq v6.4h, v8.4h, v9.4h
  cmeq v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150000000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511031611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000082258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011612200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011613200350800001002003920039200392003920039
80204200381500000000149258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
8020420038150000000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011611200350800001002003920039200392003920039
80204200381500000012040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000000511011613200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000812580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050204165620035080000102003920039200392003920039
80024200381500000392580010108000010800005064000012005820038200389996031001880010208009620160000200382003811800211091010800001000050203163520035080000102003920039200392003920039
80024200381500100392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050205165520035080000102003920039200392003920039
80024200381500000392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050205165620035080000102003920039200392003920039
80024200381500000392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050205165520035080000102003920039200392003920039
80024200381490000704258001010800001080000506400000200192003820038999603100188001020800002016000020038200381180021109101080000100012050203163520035080000102003920039200392003920039
80024200381500000392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050205165520035080000102003920039200392003920039
80024200381500000392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050205163620035080000102003920039200392003920039
80024200381500000392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050205165420035080000102003920039200392003920039
80024200381500000392580010108000010800005064000002001920038200389996031001880010208000020160000200382003811800211091010800001000050205165420035080000102003920039200392003920039