Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (register, 4S)

Test 1: uops

Code:

  cmeq v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037160821687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038203820382038
100420371612611687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038208520382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316231787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038203820382038
10042037150611687251000100010002646802018203720371572318951000100020002037203711100110000073316331787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371500063196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001271011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100671011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
10204200371501351086119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100971011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001271011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100971011611197910100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002471011611197910100001002003820038200382003820038
1020420037150906119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000010061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000038096405162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100004101506402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002008520037111002110910101000010000440636402162219785010000102003820038200382003820038
1002420037150000000010319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100002006402162219785010000102003820038200382003820038
10024200371500000000103196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000027066402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100004601566402162219785010000102003820038200382003820038
1002420037150000009061196872510010101000010100005028502460200182003720037184443187671001020100002020000200372003711100211091010100001000024006403162219785010000102003820038200382003820038
100242003715000000001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000490396402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000042006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmeq v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000025119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002018020085111020110099100100100001000071011611197910100001002003820038200382003820038
10204200371500000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000710116111979110100001002003820038200382003820038
10204200371500000012619687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001005398671011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680200182003720230184223187451010020010000200200002003720037111020110099100100100001004071011611197910100001002003820038200382003820182
1020420037150000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611198230100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680200182003720037184227187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000033001741968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003714900000001451968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000030006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000606402162219785010000102003820038200382003820038
100242003715000000006251968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000004491968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000606402162219785010000102003820038200382003820038
10024200371500000000821968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284896312001820037200851844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037150000000012781968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000306402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmeq v0.4s, v8.4s, v9.4s
  cmeq v1.4s, v8.4s, v9.4s
  cmeq v2.4s, v8.4s, v9.4s
  cmeq v3.4s, v8.4s, v9.4s
  cmeq v4.4s, v8.4s, v9.4s
  cmeq v5.4s, v8.4s, v9.4s
  cmeq v6.4s, v8.4s, v9.4s
  cmeq v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815001702580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100151106162220035800001002003920039200392003920039
80204200381500402580100100800001008011250064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392019120039
80204200381509402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392003920039
802042003815001242580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392003920039
802042003815001452580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392003920039
802042003814901032580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392003920039
802042003815002142580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392003920039
802042003815001722580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100051102162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150003925800101080000108000050640000120019200382003899963100458001020800002016000020038200381180021109101080000100050202160222003580000102003920039200392003920039
8002420038150006025800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050203160222003580000102003920039200392003920039
8002420038150006025800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050203160222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100448001020800002016000020038200381180021109101080000101350202160322003580000102003920039200392003920039
80024200381500018625800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050202160332003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000103050203160222003580000102003920039200392003920039
80024200381500012325800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050202160422003580000102003920039200392003920039
8002420038151003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100350203160222003580000102003920039200392003920039
80024200381500010425800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050202160222003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050202160232003580000102003920039200392003920039