Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (register, D)

Test 1: uops

Code:

  cmeq d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037153611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq d0, d0, d1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150096119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120066200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500053619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500246119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500025119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000007200611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006407162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000821968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmeq d0, d1, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000886119676251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002041000020020000200372003711102011009910010010000100000371011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715002406119687251010010010000100100005002847680120018200372003718422818745101002001000020020000200372003711102011009910010010000100002201073511611197910100001002008520086200852008520038
10204200371501006119687251010010010000100100005002847680120054200372003718422318745101002001000020020000200372008611102011009910010010000100120071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003714906119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006619687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmeq d0, d8, d9
  cmeq d1, d8, d9
  cmeq d2, d8, d9
  cmeq d3, d8, d9
  cmeq d4, d8, d9
  cmeq d5, d8, d9
  cmeq d6, d8, d9
  cmeq d7, d8, d9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059151004025801001128000010080000500640000020019020038200389973039996801002008000020016000020038200381180201100991001008000010000651102161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019020038200389973039996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
802042003815000402580100100800001008000050064000002001932003820038997303999680100200800002001600002003820038118020110099100100800001000010551101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019020038200389973039996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019020038200389973039996801002008000020016000020038200381180201100991001008000010012351101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019020038200389973039996801002008000020016000020038200381180201100991001008000010010051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019020038200889973039996801002008000020016000020038200381180201100991001008000010030051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019020038200389973039996801002008000020016000020038200381180201100991001008000010000051101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019020038200389973039996801002008000020016000020038200381180201100991001008000010010351101161120035800001002003920039200392003920039
8020420038150004025801001008000010080000500640000020019020038200389973039996801002008000020016000020038200771180201100991001008000010000351101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000010005022516056200350080000102003920187200392003920039
80024200381490000027125800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000000305020416043200350080000102003920039200392003920039
8002420038150000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000010605020416042200350080000102003920039200392003920039
800242003815000069039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000410305040516042200350080000102003920039200392003920039
80024200381500000039258001010800001080000506400000020019200382003899963100188001020800002016000020038200381180021109101080000100000340005020416042200350080000102003920039200392003920039
8002420038150000003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000000305020416042200350080000102003920039200392003920039
8002420038150000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000030605020416042200350080000102003920039200392003920039
8002420038150000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000050605020416024200350080000102003920039200392003920039
8002420038150000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000010605020416035200350080000102003920039200392003920039
8002420038150000003925800101080189108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000010905020416042200350080000102003920039200392003920039