Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (zero, 16B)

Test 1: uops

Code:

  cmeq v0.16b, v0.16b, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371706116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371566116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715216116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq v0.16b, v0.16b, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200106642003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715010061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000214100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
102042003715000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640416661978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018200372003718443318767100102010000221000020037200841110021109101010000100640516661978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640516651978610000102003820038200382003820038
100242003715009611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640516451978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640516561978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640616661978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018200372003718443318767100102010000201016920037200371110021109101010000100640516661978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640516551978610000102003820038200382003820038
100242003715000611968625100101010000101000050284752120018200372003718443318767100102010000201000020037200371110021109101010000100640516551978610000102003820038200382003820038
100242003715000611968625100101010000101000050284788720018200372003718443318767100102010000201000020037200371110021109101010000100640516641978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmeq v0.16b, v8.16b, #0
  cmeq v1.16b, v8.16b, #0
  cmeq v2.16b, v8.16b, #0
  cmeq v3.16b, v8.16b, #0
  cmeq v4.16b, v8.16b, #0
  cmeq v5.16b, v8.16b, #0
  cmeq v6.16b, v8.16b, #0
  cmeq v7.16b, v8.16b, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150110292580108100800081008002050064013202001902003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013202001902003820038998869989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013202001902003820038997769989801202008003220080032200382003811802011009910010080000100000011151371161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013202001902003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161220035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013202001902003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013212003902003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039
8020420038150110292580108100800081008002050064013212001902003820038997769989801202008003220080032200382003811802011009910010080000100000011151181161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100003050200102160332003580000102003920039200392003920039
80024200381500000003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050200003160222003580000102003920039200392003920039
80024200381500000003925800101080000108000050640000012001920038200389996310018800102080000208000020038200381180021109101080000100000050200002160322003580000102003920039200392003920039
80024200381500000003925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050200003160322003580000102003920039200392003920039
800242003815000002103925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050200002160222003580000102003920039200392003920039
800242003815000001503925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050200002160222003580000102003920039200392003920039
8002420038150000039603925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050200003160222003580000102003920039200392003920039
8002420038150000033903925800101080000108000050640000002001920038200389996310018800102080000208000020038200381180021109101080000100000050200002161442003580000102003920039200392003920039
8002420038150000020703925800101080000108000050640000012001920038200389996310018800102080000208000020038200381180021109101080000100000050200003160222003580000102003920039200392003920039
8002420038150000041403925800101080000108000050640000012001920038200389996310018800102080000208000020038200381180021109101080000100000050200002160442003580000102003920039200392003920039