Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (zero, 2D)

Test 1: uops

Code:

  cmeq v0.2d, v0.2d, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116862510001000100026452102018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073316221786100020382038203820382038
1004203715015616862510001000100026452102018203720371571318951000100010002037203711100110000073316231786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371506116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038
100420371606116862510001000100026452112018203720371571318951000100010002037203711100110000073316331786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq v0.2d, v0.2d, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715008219686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000407102162219791100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
1020420037150025119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
1020420037150041119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
102042003715006119686251010010010000100101505532847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038
102042003715006119686251010010010000100100005002847521120018020037200371842131874510100200100002001000020037200371110201100991001001000010000007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715002000010319686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
100242003715000000010319686451001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000736402162219786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000006402162219847010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000006402162219786010000102003820038200382003820038
10024200371500000006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200372110021109101010000100000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmeq v0.2d, v8.2d, #0
  cmeq v1.2d, v8.2d, #0
  cmeq v2.2d, v8.2d, #0
  cmeq v3.2d, v8.2d, #0
  cmeq v4.2d, v8.2d, #0
  cmeq v5.2d, v8.2d, #0
  cmeq v6.2d, v8.2d, #0
  cmeq v7.2d, v8.2d, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571502925801081008000810080020500640132120019200382003899770699898012020080032200800322003820038118020110099100100800001000011151183163420035800001002003920039200392003920039
80204200381509425801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000011151184164320035800001002003920039200392003920039
8020420038150292580108100800081008002050064013202001920038200389977069989801202008003220080032200382003811802011009910010080000100059111151185164420035800001002003920039200392003920039
80204200381502925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000011151184163320035800001002003920039200392003920039
80204200381502925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000011151184164420035800001002003920039200392003920039
80204200381502925801081008000810080020511640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185163320035800001002003920039200392003920039
80204200381502925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000011151185164320035800001002003920039200392003920039
80204200381502925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000011151182163320035800001002003920039200392003920039
80204200381502925801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000011151182163420035800001002003920039200392003920039
80204200381505025801081008000810080020500640132020019200382003899770699898012020080032200800322003820038118020110099100100800001000011151183163420035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)d9daddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500392580010108000010800005064000001200192003820038999631001880010208000020800002003820038118002110910108000010001005020002160043200350080000102003920039200392003920039
8002420038150402602580010108000010800005064075601200192003820038999631001880010208000020800002003820038118002110910108000010000005020001160033200350080000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000005020001160032200350080000102003920088200492003920039
800242003815004322580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000005020001160032200350080000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000005020002160023200350080000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000005020001160036200350080000102003920039200392003920039
800242003815002102580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000005020001160032200350080000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000005020001160023200350080000102003920039200392003920039
80024200381500392580010108000010800005064000000200192003820038999631001880010208000020800002003820038118002110910108000010000005020002160063200350080000102003920039200392003920039
80024200381500392580010108000010800005064000001200192003820038999631001880010208000020800002003820038118002110910108000010000005020001160038200350080000102003920039200392003920039