Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMEQ (zero, 4H)

Test 1: uops

Code:

  cmeq v0.4h, v0.4h, #0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
1004203715246116862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
10042037153276116862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
1004203716816116862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
1004203715014516862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
1004203715010316862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038
100420371506116862510001000100026452120182037203715713189510001000100020372037111001100000073216221786100020382038203820382038

Test 2: Latency 1->2

Code:

  cmeq v0.4h, v0.4h, #0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150003486119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150003546119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150005076119686251010010010000100100005002847521020018200372003718421318745101002001000020410000200372008411102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000636119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000666119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000516119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500008219686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640316431978610000102003820038200382003820038
10024200851500611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
1002420037149297611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752112001820037200371844331876710165201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038
10024200371500611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010100640316331978610000102003820038200382003820038
1002420037150279611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000640316331978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  cmeq v0.4h, v8.4h, #0
  cmeq v1.4h, v8.4h, #0
  cmeq v2.4h, v8.4h, #0
  cmeq v3.4h, v8.4h, #0
  cmeq v4.4h, v8.4h, #0
  cmeq v5.4h, v8.4h, #0
  cmeq v6.4h, v8.4h, #0
  cmeq v7.4h, v8.4h, #0
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200381500002729258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801600200350800001002003920039200392003920039
80204200381500000124258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100210111511801600200350800001002003920039200392003920039
80204200381501000926258010810080104100800205006409081200192003820038997769989801202008003220080032200382003811802011009910010080000100003111511801600200350800001002003920039201482009820039
80204200381500111829258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801600200350800001002003920039200392003920039
8020420038150000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801600200350800001002003920039200392003920039
8020420038150000071258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111513501600200350800001002003920139200392003920090
80204200381510001229258021010080008100800205006401321200192003820100997769989801202008003220080032200382003811802011009910010080000100010111511801600200350800001002003920039200392003920039
8020420038150000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801600200350800001002003920039200392003920039
8020420038150000071258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100010111511801600200350800001002003920039200392003920039
8020420038150000029258010810080008100800205006401321200192003820038997769989801202008003220080032200382003811802011009910010080000100000111511801603200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500000001500392580010108000010800005064000002001902003820038999603100188001020800002080000200382003811800211091010800001000000050201716166200350080000102003920039200392003920039
80024200381500000002400392580010108000010800005064000002001902003820038999603100188001020800002080000200382003811800211091010800001000000050201616166200350080000102003920039200392003920039
80024200381500000001800392580010108000010800005064000002001902003820038999602110018800102080000208000020038200381180021109101080000100000005020616616200350080000102003920039200392003920039
8002420038150000000000392580010108000010800005064000002001902003820038999603100188001020800002080000200382003811800211091010800001000000050201616616200350080000102003920039200392003920039
8002420038150000000000392580010108000010800005064000002001902003820038999603100188001020800002080000200382003811800211091010800001000000050201616166200350080000102003920039200392003920039
800242003815000000000010062580010108000010800005064000002001902003820038999603100188001020800002080000200382003811800211091010800001000000050201616136200350080000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200190200382003899960310018800102080000208000020038200381180021109101080000100000005020616616200350080000102003920039200392003920039
80024200381500000004800926258001010800001080000506400000200190200382003899960310018800102080000208000020038200381180021109101080000100000035020616616200350080000102003920039200392003920039
80024200381500000002400392580010108000010800005064000002001902003820038999603100188001020800002080000200382003811800211091010800001000000050201616616200350080000102003920039200392003920039
8002420038150000000000392580010108000010800005064000002001902003820038999603100188001020800002080000200382003811800211091010800001000000050206161616200350080000102003920039200392003920039