Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGE (register, 16B)

Test 1: uops

Code:

  cmge v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715106116872510001000100026468002018203720371572318951000100020002037203711100110000073216111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmge v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000536196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715000103196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715000631196874510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002013220038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100400640216221978510000102003820038200382003820038
1002420037150106119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100406640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100010640216221978510000102018120038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmge v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382013320038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720085111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000307101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119859100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000307101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500000103196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010010640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010003640216221978510000102003820038200382003820038
10024200371500000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100370640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010003640216221978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmge v0.16b, v8.16b, v9.16b
  cmge v1.16b, v8.16b, v9.16b
  cmge v2.16b, v8.16b, v9.16b
  cmge v3.16b, v8.16b, v9.16b
  cmge v4.16b, v8.16b, v9.16b
  cmge v5.16b, v8.16b, v9.16b
  cmge v6.16b, v8.16b, v9.16b
  cmge v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915000402580100100800001008000050064000002001902003820038997303999680100200800002001600002003820038118020110099100100800001000051103161120035800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001902003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001902003820038997303999680100200800002001600002003820038118020110099100100800001000351101161120035800001002003920039200392003920039
802042003815000402580100100800001008000050064000002001902003820038997303999680100200800002001600002003820038118020210099100100800001000051102161120035800001002003920039200392003920039
802042003815000402580100100800001008000050064227802001902003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001902003820038997303999680100200800002001600002003820038118020110099100100800001000651101161120035800001002003920039200392003920039
802042003815000402580100100800001008000050064000012001902003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000632580100100800001008000050064000002001902003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000402580100100800001008000050064000002001902003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000402580100100800001088000050064000012001902003820038997303999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)branch mispred nonspec (cb)cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004716104162580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502012516132520035080000102003920039200392003920039
80024200381610392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502002716132520035080000102003920039200392003920039
80024200381610392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502002816272620035080000102003920039200392003920039
80024200381610392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502002016271620035080000102003920039200392003920039
800242003816142392580010108000010800005064000000200192003820038999631001880010208000020160000201892003811800211091010800001010502002716261520035080000102003920039200392003920039
80024200381610392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001010502002216252520035080000102003920039200392003920039
800242003816101872580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502002616132720035080000102003920039200392003920039
800242003815001902580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502002716272120035080000102003920039200392003920039
800242003815001022580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000502002716152720035080000102003920039200392003920039
800242003815001692580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502002716143020035080000102003920039200392003920039