Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMGE (register, 2S)

Test 1: uops

Code:

  cmge v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715010316872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716015616872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002085207411100110000073116111787100020382038203820382038
1004203715216116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110002073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  cmge v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500105061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150024061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715003061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715003061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150027061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000071196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150012061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150042061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715001261196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100000640316221978510000102003820038200382003820038
100242003715003661196872510010101000010100005028476800200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221985010000102003820038200382003820038
10024200371500661196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500361196872510010101000010100005028476800200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500661196872510010101000010100005028476800200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221984010000102003820038200382003820038
100242003715001261196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  cmge v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150246119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100017101161119791100001002003820038200382003820038
1020420037150078419687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150072619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002848230120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150518219687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006404164319785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006403164419785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006403163419785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801201622003720037184443187671001020100002020000200372003711100211091010100001006404163419785010000102003820038200382003820038
1002420037150961196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006404164319785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006404164319785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006403163419785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001036404164319785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006404163419785010000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006403163419785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  cmge v0.2s, v8.2s, v9.2s
  cmge v1.2s, v8.2s, v9.2s
  cmge v2.2s, v8.2s, v9.2s
  cmge v3.2s, v8.2s, v9.2s
  cmge v4.2s, v8.2s, v9.2s
  cmge v5.2s, v8.2s, v9.2s
  cmge v6.2s, v8.2s, v9.2s
  cmge v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005915000000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511051632200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511031633200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511031633200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010010511021623200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511021623200350800001002003920039200392003920092
802042010015000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511031622200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511021623200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511031633200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511031633200350800001002003920039200392003920039
802042003815000000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511021623200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502013167420035080000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050206165920035080000102003920039200392003920039
8002420038150639258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050206165420035080000102003920039200392003920039
8002420038150639258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050209166420035080000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050205165420035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502011166520086080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502011165420035080000102003920039200392003920039
8002420087150039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001006050201116111020035080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020111611520035080000102003920039200392003920039
80024200381500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502061641020035080000102003920039200392003920039